These instructions don't pass the check[0] for conflicts between extras: rlwimi rlwimi. fishmv rldimi rldimi. [0] https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l1269
I've added all broken instructions into tests: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=0e9a5694dfe415126a8e1a32456c1f801bfebc03
Luke, I've assigned this to you since you did the actual fix and I only did some bits of analysis and discovered the issue.
(In reply to Dmitry Selyutin from comment #2) > Luke, I've assigned this to you since you did the actual fix and I only did > some bits of analysis and discovered the issue. i think i can work it out, the Idx0-3 need to have to be filtered by "None", which at the moment is getting confused with "Idx0". i need to investigate more.
i found it. * "in1/in2/in3/CR in" are all (implicitly) of type SelType.SRC * "out/out2/CR out" are all SelType.DST despite the register RA sometimes being both. i added this: for (reg, seltype, idx) in extra(reg.alias): + if keytype != seltype: # only check SRC-to-SRC and DST-to-DST + continue and the problem goes away https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=de0ebb3