https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7ffad8f72 ====================================================================== FAIL: test_37_extras_rldimi (__main__.SVSTATETestCase) [0:rldimi] ---------------------------------------------------------------------- Traceback (most recent call last): File "src/openpower/sv/trans/test_pysvp64dis.py", line 35, in _do_tst "'%s' expected '%s'" % (line, expected[i])) AssertionError: 'rldimi 3,4,56,4' != 'rldimi 3,4,56,8' - rldimi 3,4,56,4 ? ^ + rldimi 3,4,56,8 ? ^ : instruction does not match 'rldimi 3,4,56,8' expected 'rldimi 3,4,56,4'
unlikely but this might be down to the definition of mb.
ok so whilst the main test_caller_*.py all work, test_pysvp64dis.py gives these. mb is slightly odd, it is a "split field" https://libre-soc.org/openpower/isa/fixedshift/ n <- sh r <- ROTL64((RS), n) b <- mb[5] || mb[0:4] <-- m <- MASK(b, ¬n) RA <- r&m | (RA)& ¬m
start with this: echo "rldimi. 3,4,56,8" >> /tmp/test.s then run these: pysvp64asm /tmp/test.s /tmp/py.s powerpc64le-linux-gnu-as /tmp/py.s -o /tmp/test.o powerpc64le-linux-gnu-objcopy -Obinary /tmp/test.o /tmp/bin.o powerpc64le-linux-gnu-objdump -dr /tmp/test.o pysvp64dis -v /tmp/bin.o and the output is: 0: 0f c2 83 78 rldimi. r3,r4,56,8 0f c2 83 78 rldimi. r3,r4,56,16 spec rldimi. RA,RS,sh,mb Rc=1 pcode n <- sh r <- ROTL64((RS), n) b <- mb[5] || mb[0:4] m <- MASK(b, ¬n) RA <- r&m | (RA)& ¬m binary [0:8] 01111000 [8:16] 10000011 [16:24] 11000010 [24:32] 00001111 opcodes 011110---------------------011-1 PO 011110 0, 1, 2, 3, 4, 5 XO 011 27, 28, 29 Rc 1 31 RA (scalar) 00011 11, 12, 13, 14, 15 RS (scalar) 00100 6, 7, 8, 9, 10 sh 111000 30, 16, 17, 18, 19, 20 mb 010000 21, 22, 23, 24, 25, 26 now let's do "rldimi. r3,r4,56,32": 0: 2f c0 83 78 rldimi. r3,r4,56,32 2f c0 83 78 rldimi. r3,r4,56,1 spec rldimi. RA,RS,sh,mb Rc=1 pcode n <- sh r <- ROTL64((RS), n) b <- mb[5] || mb[0:4] m <- MASK(b, ¬n) RA <- r&m | (RA)& ¬m binary [0:8] 01111000 [8:16] 10000011 [16:24] 11000000 [24:32] 00101111 opcodes 011110---------------------011-1 PO 011110 0, 1, 2, 3, 4, 5 XO 011 27, 28, 29 Rc 1 31 RA (scalar) 00011 11, 12, 13, 14, 15 RS (scalar) 00100 6, 7, 8, 9, 10 sh 111000 30, 16, 17, 18, 19, 20 mb 000001 21, 22, 23, 24, 25, 26 and, ahhh mb has bit 0 in the wrong place. it looks like Operand-Decode of mb is out https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/shift_rot/shift_rot_cases.py;h=71a5ce#l159 damn, there's no "ExpectedResults".
programmerjake lkcl: it was recorded, since irclog is not run by openpowerbot: 18:09 programmerjake https://libre-soc.org/irclog/%23libre-soc.2023-06-04.log.html#t2023-06-04T22:59:32 18:09 programmerjake https://libre-soc.org/irclog/%23libre-soc.2023-06-05.log.html#t2023-06-05T09:22:06 18:09 programmerjake note i posted a commit range and ghostmansd did all the work of figuring out what he broke 18:10
(In reply to Luke Kenneth Casson Leighton from comment #3) > mb > 000001 > 21, 22, 23, 24, 25, 26 > > and, ahhh mb has bit 0 in the wrong place. > > it looks like Operand-Decode of mb is out oh! i know what it is, it was renaming __str__ to __repr__, it is the printing-conversion that is skipping the Operand-printout overriding, bypassing FieldSelectableInt and printing the underlying SelectableInt value rather than the "reordered" bits of the operand.