After this evening's meeting I produced a list of talks, sent via devlist: https://lists.libre-soc.org/pipermail/libre-soc-dev/2023-October/005717.html My proposal for a talk was to - Introduce the PowerISA spec briefly (which sections should be bookmarked for reference) - The SimpleV system (brief rundown, with references to past talks, wiki page...) - LibreSOC Extensions outlined in ls012 - (maybe) A brief demo of ISACaller, showing where to find instruction info (PowerISA spec, LibreSOC wiki page), setting unit test, and running, seeing ISACaller log. Some of this is already in my head (from recent experience), but in a month or so I'll probably be ready to make draft recordings. To give myself enough time, will aim for mid-December completion (also an excuse to try setting deadline on the tracker).
The first proposal I made a few weeks ago is titled: "Overview of LibreSOC", and the goal of this first proposal is to give a long-term plan for LibreSOC, and the reason the project getting started at all. Less significance will be given to SimpleV, as this is meant to be a short intro talk to LibreSOC as a whole (why is there a need for a fully-libre SoC, etc.). This talk should be held at the beginning of the devroom, and can be made shorter than 25min if required. I've made a second submission titled: "Introduction to SimpleV and PowerISA+SVP64", which will be focused heavily on the basics of SimpleV. Ideally this talk should occur early, so that consecutive talks by Sadoon, Luke, Jacob, etc. can get going without repeating too much. Although I recommend some repetition so that SimpleV actually sticks in people's heads. This talk should probably about 45min + 5min for Q&A. In between these two talks, we could fit someone who won't be talking about SimpleV-related work.
(In reply to Andrey Miroshnikov from comment #1) > etc.). This talk should be held at the beginning of the devroom, and can be > made shorter than 25min if required. necessary. suggest 10-15 min + 5 min Q&A / switchover. > I've made a second submission titled: "Introduction to SimpleV and > PowerISA+SVP64", which will be focused heavily on the basics of SimpleV. what are the links, always edit and cross-reference, this is standard project procedure so that information is not one-way-linked (and impossible to find) https://bugs.libre-soc.org/show_bug.cgi?id=1070#c0 > Ideally this talk should occur early, and not repeat anything already covered at FOSDEM. repeats of talks are frowned upon. *update* talks covering new material is fine. all previous talks are online and trackable here https://libre-soc.org/conferences/ > This talk should probably about 45min + 5min for Q&A. 20/25 + 5. we only have 1/2 a day. 50 mins is over 20% of available time. > In between these two talks, we could fit someone who won't be talking about > SimpleV-related work. good idea.
review (on pt) not public so publishing here unless kept EXTREMELY short and written with some care this topic was already covered 3 years ago at FOSDEM2021 and the proposal risks being a duplicate of multiple pre-existing talks. https://m.youtube.com/watch?v=7rCeNzrCB_g https://archive.fosdem.org/2021/schedule/event/libresocproject/ (duplicate talks are frowned upon / not allowed at FOSDEM, they have to be original and/or cover updates like tobias is doing. that means you need to watch the 2021 and other videos in full and ensure that the proposed material is NEW)
(In reply to Luke Kenneth Casson Leighton from comment #3) > (duplicate talks are frowned upon / not allowed at FOSDEM, they > have to be original and/or cover updates like tobias is doing. > that means you need to watch the 2021 and other videos in full > and ensure that the proposed material is NEW) Then I'd be happy to withdraw "Overview of LibreSOC", since as you've mentioned it's been covered in 2021. That leaves "Introduction to SimpleV and PowerISA+SVP64", I was hoping to go over some PowerISA assembler and SimpleV examples (HF, VF). I still think it might be useful as a short primer before the other SimpleV talks. Best to actually keep it short to about 10min+5min Q&A. This could be recorded and posted online before FOSDEM instead however. Should save about 30 min from my initial estimates.
(In reply to Andrey Miroshnikov from comment #4) > (In reply to Luke Kenneth Casson Leighton from comment #3) > > (duplicate talks are frowned upon / not allowed at FOSDEM, they > > have to be original and/or cover updates like tobias is doing. > > that means you need to watch the 2021 and other videos in full > > and ensure that the proposed material is NEW) > Then I'd be happy to withdraw "Overview of LibreSOC", since as you've > mentioned it's been covered in 2021. brief reminder in another talk, first line of overview page and say "go look at 2021 talk" is probably enough. https://libre-soc.org/openpower/sv/overview/ thec2021 talk is even *on* that page. > That leaves "Introduction to SimpleV and PowerISA+SVP64", I was hoping to go > over some PowerISA assembler and SimpleV examples (HF, VF). yes VF is pretty new and people will totally get the significance of saving on vector regsters. the FFT complex number unit test is a damn good one (canonical). a SIMD ISA which of course can only do horizontal has to waste FOUR intermediate vector registers to be "performant", because of the way you have to do real,imag = ra*ra-ri*ri, ra*ri-... something like that, it is 4 multiplies (!) just for one piece of data and in VF mode you can use SCALARS for all those temps but source from the input vector *at the current loop offset* and store likewise in the result vector at the same. if the calculation is particularly complex you could end up saving an absolutely massive amount of regs, even avoid memory spill and keep to that critical LOAD-COMPUTE-STORE
Closing this bug as this talk has been considered to be too similar to talks done in previous years (2021/2022) for submission for this year's FOSDEM.