I drafted my first proposal for a talk at FOSDEM: The Libre-SOC project has been prototyped using an Lattic ECP5 FPGA before its first [tapeout](https://libre-soc.org/180nm_Oct2020). Since then many things have changed. One big change is the use of a different controller for DDR3 controller called [gram](https://git.libre-soc.org/?p=gram.git). To get DDR3 working on the OrangeCrab many changes are needed. This talk will provide an overview on my work on libre-soc in the past two years, an overview of DDR SDRAM interfaces and the PHYs commonly found on FPGAs and some ways to debug the OrangeCrab using a (BeagleWire)[https://www.crowdsupply.com/qwerty-embedded-design/beaglewire]
brilliant tobias, submit it here well before 1st dec https://pretalx.fosdem.org/fosdem-2024/cfp
Submitted, sent mail
https://pretalx.fosdem.org/fosdem-2024/talk/review/XHGZGAZZTMSM8FC3X3SNBFM3EYEQ3NDT
(In reply to Tobias Platen from comment #3) > https://pretalx.fosdem.org/fosdem-2024/talk/review/ > XHGZGAZZTMSM8FC3X3SNBFM3EYEQ3NDT tobias i did a quick review it looks great, we do however have to cut back time as there is only half a day available and there are 10 (ten!) talks. can you manage in under 25 minutes *including 5 for questions*?
No problem for me, I can shorten my talk.