Bug 1246 - Rc=1 vector output of CRs is going solely into CR0
Summary: Rc=1 vector output of CRs is going solely into CR0
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 676
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Reported: 2024-01-07 21:27 GMT by Luke Kenneth Casson Leighton
Modified: 2024-01-07 21:27 GMT (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2024-01-07 21:27:03 GMT 
this needs fixing in power_decoder2.py

            for i, stuff in enumerate((
                ("RA", e.read_reg1, dec_a.reg_out, in1_svdec, in1_step, False),
                ("RB", e.read_reg2, dec_b.reg_out, in2_svdec, in2_step, False),
                ("RC", e.read_reg3, dec_c.reg_out, in3_svdec, in3_step, False),
                ("RT", e.write_reg, dec_o.reg_out, o_svdec, o_step, True),
                ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))):

RT and EA. also needed vector of CRs

                    with m.If(cr.sv_override == 1):  # CR0
                        offs = SVP64CROffs.CR0
                        comb += to_reg.data.eq(step+offs)