Bug 1248 - sv.creqv (and others) do not encode/decode vector reg numbers correctly
Summary: sv.creqv (and others) do not encode/decode vector reg numbers correctly
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 676
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Reported: 2024-01-08 22:36 GMT by Luke Kenneth Casson Leighton
Modified: 2024-01-08 22:36 GMT (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2024-01-08 22:36:29 GMT 
the numbering (EXTRA3) and encoding for sv.cr* operations
(5-bit) is hosed. this is not a surprise as it has never
been tested. unit test time....