Bug 136 - partitioned multiplier needs to be adapted to Dadda algorithm
Summary: partitioned multiplier needs to be adapted to Dadda algorithm
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 48
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Reported: 2019-08-31 09:28 BST by Luke Kenneth Casson Leighton
Modified: 2022-07-17 14:17 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2019-08-31 09:28:50 BST 
the wallace multiplier produces a 10-stage-long chain at 64-bit.
dadda tree multipliers use less gates.
https://github.com/jorisvr/gen_hdl_multiplier

existing code that needs converting:
https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_mul_add/multiply.py;hb=HEAD