Bug 192 - Level-shifter Cell needed (HI-to-low, low-to-HI
Summary: Level-shifter Cell needed (HI-to-low, low-to-HI
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Hardware Layout (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Jean-Paul Chaput
URL:
Depends on:
Blocks: 55
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Reported: 2020-02-29 14:26 GMT by Luke Kenneth Casson Leighton
Modified: 2020-03-02 11:06 GMT (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2020-02-29 14:26:00 GMT 
GPIO is often at one voltage (3.3v, 1.8v, 1.5v) whilst the
main processor core is at another (1.8v, 1.2v or less in lower geometries).
sometimes GPIO can run at *between* 1.8v-3.3v or between 1.2v-1.5v.
we therefore need level-shifters between the GPIO I/O pads and the
main processor core voltage, on both the input and output sides.
Comment 1 Staf Verhaegen 2020-03-02 10:35:06 GMT 
The May test chip will contain IO and level shifters.
One problem I see though is that Alliance does not seem to support multi-voltage transistors in a design.
Comment 2 Luke Kenneth Casson Leighton 2020-03-02 11:06:48 GMT 
(In reply to Staf Verhaegen from comment #1)
> The May test chip will contain IO and level shifters.

that's fantastic.

> One problem I see though is that Alliance does not seem to support
> multi-voltage transistors in a design.

jean-paul?