Bug 195 - Formal correctness framework is needed for Power ISA
Summary: Formal correctness framework is needed for Power ISA
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Formal Verification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on: 211 306 331 332 418 419
Blocks: 158
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Reported: 2020-03-02 13:13 GMT by Luke Kenneth Casson Leighton
Modified: 2022-07-21 10:43 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.032.Formal
total budget (EUR) for completion of task and all subtasks: 12000
budget (EUR) for this task, excluding subtasks' budget: 6550
parent task for budget allocation: 158
child tasks for budget allocation: 306 331 332 335 340 418 419 421
The table of payments (in EUR) for this task; TOML format:
red={amount=6550, submitted=2022-07-04, paid=2022-07-21}


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Comment 1 Luke Kenneth Casson Leighton 2022-07-04 17:17:25 BST
The Power ISA pipelines are done: ALU, Logical, CR, Branch, Shift, SPR,
Mul, Trap - this can be considered completed.