layout of the IEEE754 FPU "Function Units" needed, as part of the 180nm ASIC in bug #199. these are to be done as reuseable blocks because several FPMUL blocks, several FPSQRT blocks etc. are needed per core, and they are very large.
Jean-Paul this was at least successful and showed that a large layout
would be possible. we also did the Dependency Matrices:
and also i recall we did a manual explicit positioning of large cells,
at the top level, to see how that went, with internal positioning done
in the large sub-cells.
i think we can close this one.