coriolis2 was initially designed for small ASICs (50,000 gates). it needs significant improvements to be suitable for use with LibreSOC due to its massive size (500,000 gates). additionally, it would be useful to prepare for coriolis2 conversion and refactoring to use python3
brief notes: niolib was added and also a new router algorithm.
*huge* amount of work gone in here, including antenna, buffers, IO pad ring