Bug 205 - documentation of coriolis2 layout process for 180nm
Summary: documentation of coriolis2 layout process for 180nm
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Hardware Layout (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: http://libre-soc.org/3d_gpu/layouts/c...
Depends on:
Blocks: 138
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Reported: 2020-03-02 17:39 GMT by Luke Kenneth Casson Leighton
Modified: 2022-07-21 22:35 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.02.029.Coriolis2
total budget (EUR) for completion of task and all subtasks: 4000
budget (EUR) for this task, excluding subtasks' budget: 3800
parent task for budget allocation: 138
child tasks for budget allocation: 291
The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 3800, submitted = 2022-07-04, paid = 2022-07-21 }


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Description Luke Kenneth Casson Leighton 2020-03-02 17:39:12 GMT
this is important for maintenance purposes and for later ASICs as well as educational purposes.  the process and decisions on how the layout was done must be documented, here:
Comment 1 Luke Kenneth Casson Leighton 2022-07-04 10:05:57 BST
links to other pages added, videos, explanation of JTAG, IOring,
importance of autogeneration.