Bug 247 - Implement AMDVLK / RADV Mesa Vulkan Driver
Summary: Implement AMDVLK / RADV Mesa Vulkan Driver
Status: RESOLVED DUPLICATE of bug 140
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Milestones (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Reported: 2020-03-13 15:09 GMT by Alain D D Williams
Modified: 2020-03-13 18:13 GMT (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


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Description Alain D D Williams 2020-03-13 15:09:39 GMT
An additional Vulkan driver is to be developed, alongside Kazan, starting instead from preexisting code, AMDVLK or RADV. Decision still to be made. AMDGPU assembly to be replaced with Libre RISCV SV Vectorisation and hardware accelerated opcodes for Texture interpolation, YUV2RGB, Z buffering etc.

LLVM IR assembly portion extremely likely to be shared with Kazan.

first iteration

# Initial Software-only 3D MESA Driver
software only (SwiftShader style) 3D MESA Driver, portable (x86 etc) using non-accelerated LLVM

Budget: EUR 12000
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=251

# 3D accelerated opcodes need to be added to the POWER ISA simulator 
adding iterated support for 3D opcodes to ISA Simulator (and unit tests)

Budget: EUR 7000
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=252

# Add hardware implementations of 3D accelerated opcodes 
first iterative effort developing and adding hardware accelerated 3D opcodes to 3D MESA driver

Budget: EUR 12500
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=253

# 2nd iteration of opcodes in 3D MESA driver
A 2nd iteration of opcodes in 3D MESA driver is needed.  This involves assessing and reporting on the level of success of the first round of simulations and ease of implementability in hardware, as well as the effectiveness in number of gates, power consumption and (learning from Jeff Bush's Nyuzi work) the number of pixels processed per clock.

Budget: EUR 12500
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=254

# Second iteration round for opcodes, simulation and hardware for 3D MESA
Documentation to the level of an ISA Standards Proposal of all hardware opcodes

Budget: 6000
URL: http://bugs.libre-riscv.org/show_bug.cgi?id=255

Budget: 12000+7000+12500+6000=37500
Comment 1 Luke Kenneth Casson Leighton 2020-03-13 18:12:18 GMT

*** This bug has been marked as a duplicate of bug 140 ***