Bug 287 - corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d
Summary: corrections to commit f17100d6c435aec47b17acb188272a7e9b3cf67d
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Tobias Platen
URL:
Depends on:
Blocks:
 
Reported: 2020-04-17 17:41 BST by Luke Kenneth Casson Leighton
Modified: 2020-06-30 16:38 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2020-04-17 17:41:17 BST 
* add suitable separate unit tests for both mul and carry.
  add them as *separate commits* with a message "unit test for sim multiply"
  and "unit tests for sim carry"

* remove the whitespace added around lines 140.  ensure that there is
  only one newline (not two)

* remove the redundant brackets in these two statements:

+        if(cry_out==1):
+            if(result > 0xFFFFFFFF):

* ensure that one space is between "if" and its "test"

   if cry_out == 1:
Comment 1 Luke Kenneth Casson Leighton 2020-04-18 10:17:06 BST 
tobias, see:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-April/006019.html