Bug 298 - consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
Summary: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: All All
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2020-05-01 20:17 BST by Jacob Lifshay
Modified: 2020-05-02 00:21 BST (History)
1 user (show)

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Description Jacob Lifshay 2020-05-01 20:17:25 BST 
combines binary adder with address decoder, saving a few gate delays.
https://en.wikipedia.org/wiki/Sum-addressed_decoder
The patents appear to have expired.
Comment 1 Luke Kenneth Casson Leighton 2020-05-02 00:21:10 BST 
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006196.html