define and document, at https://libre-soc.org/180nm_Oct2020/interfaces/ a set of interfaces for a minimum viable 180nm ASIC
Oh, my bad I'm just now seeing this. Relea
Relevant Links: http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006374.html http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006372.html https://libre-soc.org/shakti/m_class/pinouts/ https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/tree/master
*** Bug 303 has been marked as a duplicate of this bug. ***
yehowshua i added a stub/starting-point ls180 https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/ls180.py;h=77c5f1f7f7923cb8292499bac189ff1ce8f3b6ff;hb=aca6d68a6159136fe1f36c6430e2ffd07da13e8c also added a stub / dummy LPC function: https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/pinfunctions.py;h=e46be8d114f00bbf571092c4e7a9ec5ece39d04b;hb=aca6d68a6159136fe1f36c6430e2ffd07da13e8c#l52 it will need its pin naming correcting, and also in ls180.py everything including LPC moving to a single column. we need to move quickly on this because Rudi is waiting for us to communicate back to him the required peripheral set, and he is experienced enough to know that we are well beyond the industry standard time for making these decisions.
OK. I'll try and have it finished by Thursday afternoon.
conversation notes from Tim (Raptor Engineering) priority: * 2x SPI master * 4x I2C master * 2x UART * 4x LPC master * EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are PC>PCIe>OpenPower mappings Quad SPI raptorengineering LPC bridge github raptorengineering ~