Bug 304 - Define minimum viable interface set for 180nm ASIC
Summary: Define minimum viable interface set for 180nm ASIC
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
: 303 (view as bug list)
Depends on:
Blocks: 383
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Reported: 2020-05-08 12:15 BST by Luke Kenneth Casson Leighton
Modified: 2020-09-30 12:28 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2020-05-08 12:15:06 BST
define and document, at https://libre-soc.org/180nm_Oct2020/interfaces/
a set of interfaces for a minimum viable 180nm ASIC
Comment 1 Yehowshua 2020-05-08 15:36:36 BST
Oh, my bad I'm just now seeing this.

Comment 3 Luke Kenneth Casson Leighton 2020-05-12 13:12:39 BST
*** Bug 303 has been marked as a duplicate of this bug. ***
Comment 4 Luke Kenneth Casson Leighton 2020-05-12 13:13:06 BST
yehowshua i added a stub/starting-point ls180


also added a stub / dummy LPC function:

it will need its pin naming correcting, and also in ls180.py everything
including LPC moving to a single column.

we need to move quickly on this because Rudi is waiting for us
to communicate back to him the required peripheral set, and he
is experienced enough to know that we are well beyond the industry
standard time for making these decisions.
Comment 5 Yehowshua 2020-05-12 13:14:24 BST
OK. I'll try and have it finished by Thursday afternoon.
Comment 6 Luke Kenneth Casson Leighton 2020-05-20 23:14:26 BST
conversation notes from Tim (Raptor Engineering)


* 2x SPI master
* 4x I2C master
* 2x UART
* 4x LPC master
* EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are PC>PCIe>OpenPower mappings

Quad SPI raptorengineering
LPC bridge github raptorengineering