define and document, at https://libre-soc.org/180nm_Oct2020/interfaces/
a set of interfaces for a minimum viable 180nm ASIC
Oh, my bad I'm just now seeing this.
*** Bug 303 has been marked as a duplicate of this bug. ***
yehowshua i added a stub/starting-point ls180
also added a stub / dummy LPC function:
it will need its pin naming correcting, and also in ls180.py everything
including LPC moving to a single column.
we need to move quickly on this because Rudi is waiting for us
to communicate back to him the required peripheral set, and he
is experienced enough to know that we are well beyond the industry
standard time for making these decisions.
OK. I'll try and have it finished by Thursday afternoon.
conversation notes from Tim (Raptor Engineering)
* 2x SPI master
* 4x I2C master
* 2x UART
* 4x LPC master
* EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are PC>PCIe>OpenPower mappings
Quad SPI raptorengineering
LPC bridge github raptorengineering