see https://bugs.libre-soc.org/show_bug.cgi?id=314#c14

this is a general technique which can be implemented on the INT and FP
regfiles as well as the Condition Registers and sub-fields of other SPRs
to provide W & R hazard protection against *portions* of a regfile.

it critically requires as a direct knock-on consequence that the protected
portion have its own read and write enable line.

thus the regfile may instead of being considered e.g. "64-bit wide" may
instead be considered 8x 8-bit wide, where 64-bit operations must request
*eight* simultaneous read/write-enable lines.

it's sufficiently comprehensive that we need to leave this off the TODO list
for now.