https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=3b9beba954a2f0f7ebefc7a731d8eddcb3705698;hb=HEAD detection of zero RA reg (src1) needs to be passed through the pipelines (via the CompUnits - see bug 336) just like B (src2) being used as an immediate. this therefore needs to be done in the pipeline unit tests (test_pipe_caller.py), qemu to check the simulation, then HDL unit tests detect RA_OR_ZERO and likewise set A to zero. a flag "a_is_zero" or such would be set in power_decode2 in the execute phase.
added the flag, https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=e0088f72dbd8b53acc587fa2ec2fb9fa4aeb17c5 commit 65aceac3fa2cdc1bc34120551c23a9dff681c02e (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu May 21 17:48:20 2020 +0100 add zero_a flag to CompALUOpSubset commit e0088f72dbd8b53acc587fa2ec2fb9fa4aeb17c5 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu May 21 17:44:21 2020 +0100 add zero_a flag to Decode2ExecuteType