Bug 345 - define POWER9 regfiles
Summary: define POWER9 regfiles
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Mac OS
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on: 352 428 351
Blocks: 346 383
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Reported: 2020-05-24 15:55 BST by Luke Kenneth Casson Leighton
Modified: 2021-04-20 14:47 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 200
budget (EUR) for this task, excluding subtasks' budget: 200
parent task for budget allocation: 383
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=200, paid=2020-08-21}


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Description Luke Kenneth Casson Leighton 2020-05-24 15:55:52 BST
a series of regfiles are needed, with different characteristics and a common API

* https://libre-soc.org/3d_gpu/architecture/regfile/
* https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD
Comment 1 Luke Kenneth Casson Leighton 2020-05-27 01:41:24 BST
added XER and CR based on new VirtualRegPort.
INT and FAST also added, based on RegFileArray

that just leaves SPRs which are massive.  may leave that for now.
Comment 2 Luke Kenneth Casson Leighton 2020-07-12 23:59:38 BST
added SPRMap which translates to internal enum mapping in hardware.
Comment 3 Luke Kenneth Casson Leighton 2020-07-29 17:08:44 BST
SPR was added as binary-addressed, alongside SPRmap.  aside from dec and tb the regfiles are now in place.