certain operations are privileged. in the decoder these need to be marked as such, and a trap raised instead. * implementation: done in PowerDecode2 * tested: OP_MFMSR - pass trap pipe * not tested: OP_MTMSRD - pass trap pipe * not tested: OP_MTMSR - pass trap pipe * not tested: OP_MTSPR - spr pipe * not tested: OP_MFSPR - spr pipe * not tested: OP_ATTN - core/issuer * tested: OP_RFID - pass trap pipe * test against qemu: not done
from https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl type privilege_level is (USER, SUPER); type op_privilege_array is array(insn_type_t) of privilege_level; constant op_privilege: op_privilege_array := ( OP_ATTN => SUPER, OP_MFMSR => SUPER, OP_MTMSRD => SUPER, OP_RFID => SUPER, others => USER ); function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0)) return boolean is begin if op_privilege(op) = SUPER then return true; elsif op = OP_MFSPR or op = OP_MTSPR then return insn(20) = '1'; else return false; end;
note in spec: • If spr0 = 0, the illegal instruction error handler is invoked. • If spr0 = 1, the system privileged instruction error handler is invoked. this needs to be done in PowerDecoder2 where the SPRMap exists
need to read MSR, add extra read port to fastregs to get it. pass in to PowerDecoder2 at issue time. also, remove nia and XerBits at same time.
commit a323d95f21b521d9fffd5ce3e180449815051d3a (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue Jul 14 13:00:19 2020 +0100 add in privileged instruction decision-making in PowerDecode2 commit 4c040d55af86f8cf94bb313aee5c5dece8fed916 (origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue Jul 14 12:43:53 2020 +0100 add MSR reading to issue FSM
commit 7ca3ae564edf139d0c4abcc5c1996cd64138a87f (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue Jul 14 14:05:38 2020 +0100 add priv instruction checking to ISACaller simulator
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD#l45 TODO: shorten function by combining cases
hmm can't use fu/spr/test/test_pipe_caller.py (or the compunit variant) because for OP_MTSPR/MFSPR calling those instructions results in the opcode being *changed* to OP_TRAP, which of course the SPR pipeline doesn't support. have to find a different way (global tests on the full compunit suite, test_core.py, test_issuer.py etc.)