Bug 370 - need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
Summary: need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side
Status: RESOLVED DUPLICATE of bug 686
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Mac OS
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2020-06-08 19:34 BST by Luke Kenneth Casson Leighton
Modified: 2021-09-07 14:58 BST (History)
3 users (show)

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Description Luke Kenneth Casson Leighton 2020-06-08 19:34:03 BST 
see bug #368 - we need a way to run different POWER9 cycle-accurate execution 
environments side-by-side, in order to be able to compare them and see if they
produce the same results.  this would include native program execution on the
Raptor sponsored TALOS-II server, using gdb (native) rather than gdb (to qemu-ppc)
Comment 1 Michael Nolan 2020-06-08 19:52:51 BST 
Cycle accurate - as in checking that the results are the same after every step?
Comment 2 Luke Kenneth Casson Leighton 2020-06-08 23:03:38 BST 
(In reply to Michael Nolan from comment #1)
> Cycle accurate - as in checking that the results are the same after every
> step?

cycle-accurate means that yes, you _could_ check that the results are the
same after every step through each and every instruction (not that you absolutely
have to: it's just that it's possible to do so).

a JIT compiler (pearpc's JIT, qemu JIT) that is very specifically *not*
guaranteed to be the case, because several emulated instructions can end up being
replaced by one (optimised) sequence of host-native instructions.

JIT-translated code would clearly be absolutely useless for us to attempt to
run and compare against, for that reason.

spike (the RISC-V simulator) went to a lot of trouble to even maintain
cycle-accurate emulation of the PTW, the MMU - pretty much everything,
*specifically* so that the software (BBL, linux kernel etc.) could be worked on
in parallel with development of some hardware, and the specification formalised
even before that.
Comment 3 Luke Kenneth Casson Leighton 2020-06-09 23:08:49 BST 
powerpc64-linux-gnu-gdb -interpreter=mi
~-data-list-register-names
^done,register-names=["r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","r16","r17","r18","r19","r20","r21","r22","r23","r24","r25","r26","r27","r28","r29","r30","r31","f0","f1","f2","f3","f4","f5","f6","f7","f8","f9","f10","f11","f12","f13","f14","f15","f16","f17","f18","f19","f20","f21","f22","f23","f24","f25","f26","f27","f28","f29","f30","f31","pc","msr","cnd","lr","cnt","xer","fpscr","mq"

that should do the trick.  we can get at MSR, CR0-7 (cnd), XER, PC, LR, cnt is probably CTR, mq i have no idea.
Comment 4 Luke Kenneth Casson Leighton 2021-09-07 14:58:15 BST 

*** This bug has been marked as a duplicate of bug 686 ***