Bug 403 - runtime configureable LoadStoreUnit needed
Summary: runtime configureable LoadStoreUnit needed
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Michael Nolan
URL:
Depends on:
Blocks: 393
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Reported: 2020-06-24 15:56 BST by Luke Kenneth Casson Leighton
Modified: 2020-06-30 13:37 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2020-06-24 15:56:58 BST
minerva cli.py is capable of specifying at runtime what to "make".
we need similar capability at strategic interfaces in order to
carry out different levels of testing without other code (untested
or just too much of it) being in the way.

a class is therefore needed that selects between

* TestMemoryLoadStoreUnit
* BareLoadStoreUnit
* CacheLoadStoreUnit
* others (to be added)
Comment 1 Luke Kenneth Casson Leighton 2020-06-25 11:28:42 BST
michael are you sure this is resolved, i didn't see a commit? did you remember
to "git add"?

forgot to add cross-ref:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008354.html

basic principle:

class ConfigureableLoadStoreUnit:
    def __init__(self, ifacetype, *args, **kwargs):
        if ifacetype == "testmem":
            self.lsi = TestMemoryLoadStoreUnit(*args, **kwargs)
        elif ifacetype == "bare_wb":
            self.lsi = BareLoadStoreUnit(*args, **kwargs)
        elif ifacetype == "cache_wb":
            self.lsi = CacheLoadStoreUnit(*args, **kwargs)
Comment 2 Luke Kenneth Casson Leighton 2020-06-26 11:37:31 BST
apologies, michael, i didn't hear back from you, had to move on:

[master c88f971] add reconfigureable Load/Store class