Bug 416 - dec and tb POWER9 SPRs needed
Summary: dec and tb POWER9 SPRs needed
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: High enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 383
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Reported: 2020-07-05 17:49 BST by Luke Kenneth Casson Leighton
Modified: 2021-12-09 13:41 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 200
budget (EUR) for this task, excluding subtasks' budget: 200
parent task for budget allocation: 383
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 200, submitted = 2020-12-06, paid = 2020-12-06 }

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Description Luke Kenneth Casson Leighton 2020-07-05 17:49:54 BST 
-- FIXME: run at 512MHz not core freq
ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
Comment 1 Luke Kenneth Casson Leighton 2020-07-05 17:53:59 BST 
interrupt when dec reaches -1

	if ctrl.msr(MSR_EE) = '1' then
	    if ctrl.dec(63) = '1' then
		v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
		report "IRQ valid: DEC";
		irq_valid := '1';
Comment 2 Luke Kenneth Casson Leighton 2020-09-06 12:56:58 BST 
commit a645950fa2d3c64b63b187485034dbafd115a16d (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sun Sep 6 12:13:16 2020 +0100

    add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt

commit ee491651861ed89c44ced180189656b8a80fbee0 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sun Sep 6 12:50:47 2020 +0100

    move DEC and TB from StateRegs to FastRegs for several reasons
    first: SPR pipeline already has fast1 read/write
    second: a new DecodeStateIn/Out object would be needed
            instead just add FastRegs.DEC/TB to DecodeA/Out
    third: there is probably a third somewhere

commit 0df522b99d98618d9ff5f95f622dbd79267ae728 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sun Sep 6 12:56:48 2020 +0100

    add a DEC/TB FSM to TestIssuer
    
    this operates on alternative cycles, because it reads/writes from the
    Fast Regfile directly
Comment 3 Luke Kenneth Casson Leighton 2020-09-06 19:56:59 BST 
litex sim running microwatt tests/decrementer/decrementer.bin passes

[clocker] sys_clk: freq_hz=1000000, phase_deg=0
Test 01:PASS
Test 02:PASS
Test 03:PASS