Bug 442 - Convert comp_unit_req_rel diagram to SVG
Summary: Convert comp_unit_req_rel diagram to SVG
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Documentation (show other bugs)
Version: unspecified
Hardware: PC Linux
: Low enhancement
Assignee: Cole Poirier
URL:
Depends on:
Blocks:
 
Reported: 2020-07-27 19:44 BST by Cole Poirier
Modified: 2021-02-08 10:16 GMT (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 389
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Attachments
Original bitmap comp_unit_req_rel (30.08 KB, image/jpeg)
2020-07-27 19:44 BST, Cole Poirier
Details
Diagram comp_unit_req_rel D1 SVG (9.28 KB, image/svg+xml)
2020-07-27 19:45 BST, Cole Poirier
Details
Diagram comp_unit_req_rel D1 SVG (22.94 KB, image/svg+xml)
2020-07-27 19:49 BST, Cole Poirier
Details
Diagram comp_unit_req_rel D1 PNG (33.22 KB, image/png)
2020-07-27 19:49 BST, Cole Poirier
Details
Diagram comp_unit_req_rel D2 SVG (35.92 KB, image/svg+xml)
2020-07-27 19:52 BST, Cole Poirier
Details
Diagram comp_unit_req_rel D2 PNG (48.81 KB, image/png)
2020-07-27 19:54 BST, Cole Poirier
Details
comp_unit_req_rel.svg (22.32 KB, image/svg+xml)
2020-10-20 23:20 BST, Umberto Cerrato
Details
New comp_unit_req_rel SVG image (31.14 KB, image/svg+xml)
2020-10-28 13:13 GMT, Umberto Cerrato
Details
"isa_to_virtual_regs_tabl" initial sketch (7.21 KB, image/gif)
2021-02-08 10:16 GMT, Umberto Cerrato
Details

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Description Cole Poirier 2020-07-27 19:44:05 BST
Created attachment 79 [details]
Original bitmap comp_unit_req_rel

Convert bitmap comp_unit_req_rel diagram to SVG
Comment 1 Cole Poirier 2020-07-27 19:45:15 BST
Created attachment 80 [details]
Diagram comp_unit_req_rel D1 SVG

First draft missing labels
Comment 2 Cole Poirier 2020-07-27 19:49:12 BST
Created attachment 81 [details]
Diagram comp_unit_req_rel D1 SVG

Resized D1 svg so it fits in the view box
Comment 3 Cole Poirier 2020-07-27 19:49:37 BST
Created attachment 82 [details]
Diagram comp_unit_req_rel D1 PNG
Comment 4 Cole Poirier 2020-07-27 19:52:39 BST
Created attachment 83 [details]
Diagram comp_unit_req_rel D2 SVG

Added all labels except for three that are illegible in the bit map. Luke, can you tell me what the illegible labels that look like they spell out "cl_one" actually are? They are the labels in vertical alignment with the three corresponding "op_en" labels.
Comment 5 Cole Poirier 2020-07-27 19:54:56 BST
Created attachment 84 [details]
Diagram comp_unit_req_rel D2 PNG

(don't upload PNGs when doing SVG)
Comment 6 Umberto Cerrato 2020-10-20 23:20:13 BST
Created attachment 110 [details]
comp_unit_req_rel.svg
Comment 7 Umberto Cerrato 2020-10-28 13:13:58 GMT
Created attachment 112 [details]
New comp_unit_req_rel SVG image

This is the new image with the Wikimedia logic ports SVGs (modified).
Comment 8 Umberto Cerrato 2021-02-08 10:16:01 GMT
Created attachment 124 [details]
"isa_to_virtual_regs_tabl" initial sketch

This is the part on the right of the original image.
The blue circle and arrow indicate a node I made; but looking at the original image I am not sure it should go there. Looking at the little drawing on the left, I think it should go on the vertical wire on the right. But I think you can quickly help me found out this.