Bug 470 - convert code using LoadStoreInterface to PortInterface
Summary: convert code using LoadStoreInterface to PortInterface
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 383
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Reported: 2020-08-20 11:54 BST by Luke Kenneth Casson Leighton
Modified: 2021-12-12 23:47 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
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Description Luke Kenneth Casson Leighton 2020-08-20 11:54:35 BST
the converter pi2ls.py unfortunately involves an additional FSM that is
overhead (and causing problems).  a version of BareLoadStoreUnit is
needed that complies to PortInterface and accesses the wishbone bus
directly.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/pimem.py;hb=HEAD#l35

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/loadstore.py;hb=HEAD#l13

also the Instruction Fetch unit can at some point be converted as well
although it is not as high priority as it is working.

the same unit tests currently in place can be used that are currently
testing PortInterface into small wishbone SRAM