the converter pi2ls.py unfortunately involves an additional FSM that is
overhead (and causing problems). a version of BareLoadStoreUnit is
needed that complies to PortInterface and accesses the wishbone bus
also the Instruction Fetch unit can at some point be converted as well
although it is not as high priority as it is working.
the same unit tests currently in place can be used that are currently
testing PortInterface into small wishbone SRAM