Bug 471 - bug in modsd DIV FSM
Summary: bug in modsd DIV FSM
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: Highest enhancement
Assignee: Jacob Lifshay
URL:
Depends on:
Blocks: 324 383
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Reported: 2020-08-22 14:01 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-14 19:31 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.043.Wishbone
total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100
parent task for budget allocation: 383
child tasks for budget allocation:
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jacob={amount=100,paid=2020-12-09}

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Description Luke Kenneth Casson Leighton 2020-08-22 14:01:13 BST 
+    # modulo
+    def case_modsd_regression(self):
+        lst = [f"modsd 17, 27, 0"]
+        initial_regs = [0] * 32
+        initial_regs[0] = 0xff
+        initial_regs[27] = 0x7fffffffffffffff
+        with Program(lst, bigendian) as prog:
+            self.add_case(prog, initial_regs)
+
Comment 1 Luke Kenneth Casson Leighton 2020-08-22 14:02:36 BST 
commit b383af53f538aab1dccc7ea9950ffb300a1f5c45 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sat Aug 22 14:01:26 2020 +0100

    modsd bug, https://bugs.libre-soc.org/show_bug.cgi?id=471
Comment 2 Luke Kenneth Casson Leighton 2020-08-22 14:14:34 BST 
the pipeline calculates this one correctly, as does DivSIM:

check extra output. "DivPipeCore: modsd 17, 27, 0 'modsd 17, 27, 0\\n' [255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9223372036854775807, 0, 0, 0, 0]" 0 0

pia also gets it right:

>>> 0x7fffffffffffffff % 255
>>> 127

however this might also be a bug in microwatt (urrr)
Comment 3 Luke Kenneth Casson Leighton 2020-08-22 15:53:35 BST 
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000205.html

jacob this one's stopping me from being able to do comparisons on microwatt.
i've a second case (this time divsd) which is producing incorrect results
Comment 4 Luke Kenneth Casson Leighton 2020-08-22 16:07:52 BST 
commit dea6484bf446242dc049905f7a8babfdefad13bb (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sat Aug 22 16:07:22 2020 +0100

    moved to div pipe temporarily in compunits
Comment 5 Luke Kenneth Casson Leighton 2020-08-22 18:57:59 BST 
(In reply to Luke Kenneth Casson Leighton from comment #4)
> commit dea6484bf446242dc049905f7a8babfdefad13bb (HEAD -> master)
> Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> Date:   Sat Aug 22 16:07:22 2020 +0100
> 
>     moved to div pipe temporarily in compunits

git pull on ieee754fp, *might* now be getting correct results from
DivPipe

commit dc9082559f7fba8555c2f76a6de95a6d84a6d087 (HEAD -> master, origin/master)
Author: Jacob Lifshay <programmerjake@gmail.com>
Date:   Sun Jul 19 20:19:22 2020 -0700

    disable faulty bit_width reduction logic in DivPipeCore
Comment 6 Jacob Lifshay 2020-08-26 19:31:03 BST 
AFAIK the bug was fixed by the following commit:
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=a55449dd50d6a1658aec74625b3cbdb0fa17e8f9
Comment 7 Luke Kenneth Casson Leighton 2020-08-26 19:33:51 BST 
i've still a simulator bug to track, found one yesterday, the other todo. i'll close when confirmed.