Bug 493 - DMI JTAG TAP needed
Summary: DMI JTAG TAP needed
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: Normal normal
Assignee: Cole Poirier
URL:
Depends on:
Blocks: 383 414 490
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Reported: 2020-09-16 19:43 BST by Cole Poirier
Modified: 2021-05-05 21:45 BST (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 400
budget (EUR) for this task, excluding subtasks' budget: 400
parent task for budget allocation: 383
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"colepoirier" = {amount=150, paid=2021-05-05} "lkcl" = {amount=250, submitted=2020-12-06}


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Comment 1 Luke Kenneth Casson Leighton 2020-09-21 14:56:15 BST
rright, turns out microwatt DMI to JTAG was not "low-level" enough
(relying on an FSM from Xilinx) so had to derive from Chips4Makers
TAG class.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi2jtag.py;hb=HEAD

very basic unit test passes, shows that ID can be read.  next step
is to add DMI unit test
Comment 2 Luke Kenneth Casson Leighton 2020-09-21 17:31:08 BST
commit fd902da6f694e68a4c664786fd02857866d90d3e (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon Sep 21 16:44:41 2020 +0100

    experiment set dmi msr read

commit 93d363b8ce543230ac3f2df9859337ce0f2691e3
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon Sep 21 16:37:20 2020 +0100

    add DMI JTAG test
Comment 3 Luke Kenneth Casson Leighton 2020-09-22 17:08:59 BST
https://www2.lauterbach.com/pdf/training_jtag.pdf

this says, "Reading or writing the IR or DR is performed bitwise from LSB to MSB. With every bit shifted into the TAP controller via TDI, the contents of DR is rightshifted one bit, providing the LSB on TDO."

this seems to be ok:

            # tdo = reg[0], tdo_en = shift
            tdos.append((reg[0], sr_shift))

and yes, this seems to be ok:

                m.d.posjtag += reg.eq(Cat(reg[1:], self.bus.tdi))

however this seems anomalous in TAP._elaborate_ios():

        with m.Elif(shift):
            m.d.posjtag += io_sr.eq(Cat(self.bus.tdi, io_sr[:-1]))

ah.  right.

http://openocd.org/doc/html/TAP-Declaration.html

-ircapture NUMBER

The bit pattern loaded by the TAP into the JTAG shift register on entry to the IRCAPTURE state, such as 0x01. JTAG requires the two LSBs of this value to be 01. By default, -ircapture and -irmask are set up to verify that two-bit value. You may provide additional bits if you know them, or indicate that a TAP doesn’t conform to the JTAG specification.

so this, if i am reading it correctly, indicates that when you "set" the IDCODE shift register, it must have been pre-loaded with a default value of 0b00001

the *old* (previous) shift-ir must have been set (at reset) to "0b000001".

where at present i am finding that it is *all* 1s.
Comment 4 Luke Kenneth Casson Leighton 2020-12-06 13:20:53 GMT
happy with this.
Comment 5 Cole Poirier 2020-12-06 23:29:02 GMT
(In reply to Luke Kenneth Casson Leighton from comment #4)
> happy with this.

Yes.