498 – JTAG ECP5 "tap" needed

Bug 498 - JTAG ECP5 "tap" needed

Summary: JTAG ECP5 "tap" needed

Status:	CONFIRMED

Alias:	None

Product:	Libre-SOC's first SoC
Classification:	Unclassified
Component:	Source Code (show other bugs)
Version:	unspecified
Hardware:	PC Linux

Importance:	Low enhancement
Assignee:	Luke Kenneth Casson Leighton

URL:

Depends on:
Blocks:	383
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Reported:	2020-09-22 13:29 BST by Luke Kenneth Casson Leighton
Modified:	2020-09-22 13:29 BST (History)
CC List:	1 user (show)

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Description Luke Kenneth Casson Leighton 2020-09-22 13:29:38 BST

https://raw.githubusercontent.com/Spritetm/hadbadge2019_fpgasoc/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v
https://github.com/emard/ulx3s-misc/blob/27338b0081b3b441f2fa77769350fa777bd3bcf9/examples/jtag_slave/hdl/top/top_jtagg_slave.v
https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/4ae8277c45e17e316bb4d46ce625c1507506cd36/soc/top_fpga.v

examples of how to "tap" into the (undocumented) JTAGG port on an ECP5.
this is very similar to Xilinx BSCANE2