Bug 508 - decide package size and pin allocation for 180nm ASIC
Summary: decide package size and pin allocation for 180nm ASIC
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Hardware Layout (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 199 383 490
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Reported: 2020-09-30 12:31 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-06 13:37 GMT (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.Coriolis2
total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100
parent task for budget allocation: 199
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=50, submitted=2020-12-06} "staf"={amount=50}


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Description Luke Kenneth Casson Leighton 2020-09-30 12:31:41 BST
picked:  https://www.greatek.com.tw/product6-en.html

* 14x20 body size
* 0.5mm pitch QFP-128
* lead-length 1.6mm
* no need for the EP.


the package size needs to be decided for the
180nm test ASIC.  also the pin allocation currently auto-generated here:

https://libre-soc.org/180nm_Oct2020/ls180/

code here:

https://git.libre-soc.org/?p=pinmux.git;a=blob;f=src/spec/ls180.py;hb=HEAD
Comment 1 Luke Kenneth Casson Leighton 2020-09-30 12:36:46 BST
staf based on what you said in the meeting last week i remember "QFP-128"
so i based ls180.py on that.  there are around 32 unused (NC) pins meaning
that in theory a QFP-100 could be done.

however i recall that you said you have a preferred standard package size
(QFP-128) and am perfectly happy to go with that.

i have currently set 8x VDD, 8x VSS however there is weirdness in coriolis,
i have no idea what vddick / vddeck are, these appear to be wired to the
VSS/VDD of the actual pads (a separate power supply for the pads themselves?)
Comment 2 Staf Verhaegen 2020-09-30 13:04:18 BST
We should at least be able to pick any one of the packages listed here:
https://www.greatek.com.tw/product6-en.html
Comment 3 Luke Kenneth Casson Leighton 2020-09-30 13:36:44 BST
(In reply to Staf Verhaegen from comment #2)
> We should at least be able to pick any one of the packages listed here:
> https://www.greatek.com.tw/product6-en.html

ya with you.  ahh... can we pick a JEDEC package? i'd recommend MS-022
https://www.nxp.com/docs/en/package-information/SOT320-2.pdf

* QFP-128
* 28mm x 28mm
* 0.8mm pin pitch

0.8mm pitch pins are chunky and easy to do with a hot-air gun.

that ok with you?  or do we have to go with Greatek Electronic?

those Greatek Electronic ones look... specialised.   0.4 to 0.6mm pin
pitch is... tricky to solder if you have to do it by hand.  plus, their
128s are not a square package.
Comment 4 Staf Verhaegen 2020-09-30 14:20:52 BST
We have to go with a Graetek one as these have existing wireframes. Otherwise one need to pay tooling for getting your own wireframe and this a few $10K and not accounted for in the NLNet budget.
Other packagers imec has access to typically don't want to be bothered with low volumes.
Comment 5 Luke Kenneth Casson Leighton 2020-09-30 15:21:57 BST
(In reply to Staf Verhaegen from comment #4)
> We have to go with a Graetek one as these have existing wireframes.

blech, ok.

> Otherwise one need to pay tooling for getting your own wireframe and this a
> few $10K and not accounted for in the NLNet budget.
> Other packagers imec has access to typically don't want to be bothered with
> low volumes.

ok then the 14x20 body size, 0.5mm pitch QFP-128 lead-length 1.6mm, no
need for the EP.

is it best to do an io ring that roughly matches that?

N: 38
S: 38
E: 26
W: 26

or can we get away with 32-32-32-32?
Comment 6 Jacob Lifshay 2020-09-30 17:38:59 BST
I didn't check which packages have what, but I think we should get a package with a metal bottom since our test chip could use a few watts at 300MHz and be harder to cool in just a plastic package. I'm assuming the cost of the packages is small enough to be negligible.
Comment 7 Staf Verhaegen 2020-09-30 17:42:21 BST
> is it best to do an io ring that roughly matches that?
> 
> N: 38
> S: 38
> E: 26
> W: 26
> 
> or can we get away with 32-32-32-32?

The inner lead frame has 32 IO connections on each side so the latter.
Comment 8 Luke Kenneth Casson Leighton 2020-09-30 18:04:01 BST
(In reply to Jacob Lifshay from comment #6)
> I didn't check which packages have what, but I think we should get a package
> with a metal bottom

Exposed Pad.

> since our test chip could use a few watts at 300MHz and
> be harder to cool in just a plastic package. I'm assuming the cost of the
> packages is small enough to be negligible.

mmm except it is "pin 129" (usually connected to GND) and we'd have to find out
how that's wired up.  or if it's safe to ignore.  or if it affects how the
ioring must be organised (33-32-32-32)?

then communicate that to jean-paul, who would need to tell us if it can
be supported in coriolis2, and how, and how much time it would take.

something as simple as "which package" has so many implications!

bottom line, if we have to run at a lower speed then this is less risk
than trying to add extra time which we may not have.  the heat can be
"solved" with the application of some coolant spray... :)
Comment 9 Luke Kenneth Casson Leighton 2020-09-30 18:04:54 BST
(In reply to Staf Verhaegen from comment #7)

> > or can we get away with 32-32-32-32?
> 
> The inner lead frame has 32 IO connections on each side so the latter.

excellent.  no redesign work of ioring.py needed or the pinmux ls180.py