Bug 511 - Add a test of IO pins to debug/test/test_jtag_tap.py
Summary: Add a test of IO pins to debug/test/test_jtag_tap.py
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: Normal normal
Assignee: Cole Poirier
URL:
Depends on:
Blocks: 383
  Show dependency treegraph
 
Reported: 2020-10-05 02:58 BST by Cole Poirier
Modified: 2020-10-26 00:16 GMT (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Wishbone
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation: 383
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Description Cole Poirier 2020-10-05 02:58:14 BST
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000697.html


``` lkcl
Add a test of IO pins to debug/test/test_jtag_tap.py.  i *think*
these are "standard-defined JTAG behaviour".  need to work out the
code (or find IEEE JTAG documentation)

some commands here:
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L344

and here you can see the Muxes being created:
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/c4m/nmigen/jtag/tap.py#L443

JTAG Boundary scan it's officially called.
https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/nmigen/cocotb/controller/test.py#L99"

yep that needs converting to nmigen.
```
Comment 1 Luke Kenneth Casson Leighton 2020-10-06 20:42:42 BST
needs to be a stand-alone test similar to debug/test/test_jtag_tap.py
except not like this:

    iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
    ios = [dut.add_io(iotype=iotype) for iotype in iotypes]

using class JTAG as the starting point with a pinset = dummy_pinset()
(see debug/jtag.py) the test needs to use jtag_read_write_reg() to
set the shift IR to 0 (SAMPLEPRELOAD) or 2 (EXTEST) as appropriate
and also set up the appropriate JTAG.io[0..3] records before doing
so.
Comment 2 Luke Kenneth Casson Leighton 2020-10-08 16:25:35 BST
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=ffd02617c02cde6b9862def7c0f55088c116ad73

first sort-of test and it seems to partly work.  needs investigating.
Comment 3 Cole Poirier 2020-10-08 19:38:25 BST
(In reply to Luke Kenneth Casson Leighton from comment #2)
> https://git.libre-soc.org/?p=soc.git;a=commitdiff;
> h=ffd02617c02cde6b9862def7c0f55088c116ad73
> 
> first sort-of test and it seems to partly work.  needs investigating.

Sure, what should I investigate?
Comment 4 Luke Kenneth Casson Leighton 2020-10-08 23:32:22 BST
(In reply to Cole Poirier from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > https://git.libre-soc.org/?p=soc.git;a=commitdiff;
> > h=ffd02617c02cde6b9862def7c0f55088c116ad73
> > 
> > first sort-of test and it seems to partly work.  needs investigating.
> 
> Sure, what should I investigate?

don't know.  can you at least run it, successfully?  i'm staring at the c4m files and not spotting anything obvious.  the c4m cocotb unit tests clearly work.

this is the equivalent test:

https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/nmigen/cocotb/controller/test.py#L97

the ioconn pads/core values should match up, and they don't.
Comment 5 Luke Kenneth Casson Leighton 2020-10-08 23:34:36 BST
doh...


commit 8f03e6cc3e6dda74f0725a76a2982ec669ff9423 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Thu Oct 8 23:34:23 2020 +0100

    missing yields in JTAG pads test to allow settling
Comment 6 Luke Kenneth Casson Leighton 2020-10-08 23:40:17 BST
still not quite right: ioconn3.core.i is inverted.
hm
Comment 7 Cole Poirier 2020-10-09 19:06:19 BST
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Cole Poirier from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #2)
> > > https://git.libre-soc.org/?p=soc.git;a=commitdiff;
> > > h=ffd02617c02cde6b9862def7c0f55088c116ad73
> > > 
> > > first sort-of test and it seems to partly work.  needs investigating.
> > 
> > Sure, what should I investigate?
> 
> don't know.  can you at least run it, successfully?  i'm staring at the c4m
> files and not spotting anything obvious.  the c4m cocotb unit tests clearly
> work.
> 
> this is the equivalent test:
> 
> https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/nmigen/cocotb/
> controller/test.py#L97
> 
> the ioconn pads/core values should match up, and they don't.

Nope.. :( I spent all of last night trying to get it to work but the code is out-of-date compared to it's dependency cocotbext-wishbone, sent message on list, need assistance.
Comment 8 Cole Poirier 2020-10-20 21:00:30 BST
(In reply to Luke Kenneth Casson Leighton from comment #6)
> still not quite right: ioconn3.core.i is inverted.
> hm

Any tips on how I should start debugging this to find the source of the error/why the ioconn3.core.i signal is inverted? Should I familiarize myself with the JTAG spec? I started trying to debug this one day last week and was looking through the code in debug and debug/test, as well as trying to figure out the correspondence between your code and staf's c4m-jtag code using the asserts as reference points.
Comment 9 Luke Kenneth Casson Leighton 2020-10-20 21:23:18 BST
(In reply to Cole Poirier from comment #8)

> Any tips on how I should start debugging this to find the source of the
> error/why the ioconn3.core.i signal is inverted? Should I familiarize myself
> with the JTAG spec? I started trying to debug this one day last week and was
> looking through the code in debug and debug/test, as well as trying to
> figure out the correspondence between your code and staf's c4m-jtag code
> using the asserts as reference points.

look through the code, compare it with the gtkwave diagrams, hunt for the
shift registers being set.

it will be easier to (temporarily) comment out everything but the set/get
of the IOconn.

also perhaps Cesar could help take a look?
Comment 10 Cole Poirier 2020-10-20 21:38:27 BST
(In reply to Luke Kenneth Casson Leighton from comment #9)
> (In reply to Cole Poirier from comment #8)
> 
> > Any tips on how I should start debugging this to find the source of the
> > error/why the ioconn3.core.i signal is inverted? Should I familiarize myself
> > with the JTAG spec? I started trying to debug this one day last week and was
> > looking through the code in debug and debug/test, as well as trying to
> > figure out the correspondence between your code and staf's c4m-jtag code
> > using the asserts as reference points.
> 
> look through the code, compare it with the gtkwave diagrams, hunt for the
> shift registers being set.
> 
> it will be easier to (temporarily) comment out everything but the set/get
> of the IOconn.
> 
> also perhaps Cesar could help take a look?

That's super helpful, thank you! Oooh the honour of having Cesar's help is not something I would ever pass up :)
Comment 11 Cesar Strauss 2020-10-20 22:48:45 BST
(In reply to Cole Poirier from comment #10)
> (In reply to Luke Kenneth Casson Leighton from comment #9)
> > also perhaps Cesar could help take a look?
> 
> That's super helpful, thank you! Oooh the honour of having Cesar's help is
> not something I would ever pass up :)

Sure, I'll help.

I started by taking a look at the traces in dmi2jtag_test_srv.vcd, generated by ~/src/soc/src/soc/debug/test/test_jtag_tap_srv.py
Comment 12 Cesar Strauss 2020-10-21 17:30:48 BST
I found something suspicious. The testbench first writes values to some signals, treating them as inputs:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap_srv.py;h=ff3d330c271ba38af873ea51f82024467988c2d5;hb=HEAD#l65

Then, it reads from the same signals, as if they were outputs:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap_srv.py;h=ff3d330c271ba38af873ea51f82024467988c2d5;hb=HEAD#l78

According to the cocotb testbench (https://gitlab.com/Chips4Makers/c4m-jtag/-/blob/master/test/nmigen/cocotb/controller/test.py#L122),
the testbench is supposed to write to: *_pad__i, *_core__o and *_core__oe,
and then read from: *_core__i, *_pad__o and *_pad__oe.

The writing part seems OK, but the reading part is wrong. Some of the core/pad pairs are exchanged with respect to the cocotb testbench.
Comment 13 Luke Kenneth Casson Leighton 2020-10-21 17:47:59 BST
brilliant, cesar, that was it.  ok happy to have this confirmed.

commit f79171c616332622b51ef96b4f69ec46883855bc (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Wed Oct 21 17:47:15 2020 +0100

    fix up asserts (check correct pads/cores)
Comment 14 Cole Poirier 2020-10-21 18:33:55 BST
(In reply to Luke Kenneth Casson Leighton from comment #13)
> brilliant, cesar, that was it.  ok happy to have this confirmed.
> 
> commit f79171c616332622b51ef96b4f69ec46883855bc (HEAD -> master)
> Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> Date:   Wed Oct 21 17:47:15 2020 +0100
> 
>     fix up asserts (check correct pads/cores)

Did you forget to push your commit? Last update to the soc repo was about a day ago. Not seeing this commit there.
Comment 15 Luke Kenneth Casson Leighton 2020-10-21 22:25:21 BST
(In reply to Cole Poirier from comment #14)

> Did you forget to push your commit? 

evidently yes :)
Comment 16 Cole Poirier 2020-10-21 22:43:01 BST
(In reply to Luke Kenneth Casson Leighton from comment #15)
> (In reply to Cole Poirier from comment #14)
> 
> > Did you forget to push your commit? 
> 
> evidently yes :)

Glad to have the commit now as now we can do yet more debugging!

I'm a bit confused by your commit. It looks like you're changing the values, for the print statements from ("pad.i", yield xxx.pad.i) to ("pad.i", yield xxx.core.i)... How is it that the value of pad.i is actually that of core.i?

Also, it looks like we need some more help from Cesar as the tests still fail.

```
python3 test_jtag_tap.py 
idcode 0x18ff
        dmi wen, addr 0 0
        read ctrl reg 4
dmi ctrl status 0x4
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 4
dmi ctrl status 0x4
        dmi wen, addr 1 0
        write ctrl reg 5 6
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 6
dmi ctrl status 0x6
Traceback (most recent call last):
[snip]
  File "test_jtag_tap.py", line 118, in jtag_sim
    assert status == 0
AssertionError
```

```
python3 test_jtag_tap_srv.py server (talking to `python3 test_jtag_tap.py`)
running server only as requested, use openocd remote to test
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 1 0
        write ctrl reg 3 6
        dmi wen, addr 0 1
        dmi wen, addr 0 1
        dmi wen, addr 0 2
        dmi wen, addr 0 0
        read ctrl reg 6
        dmi wen, addr 1 0
        write ctrl reg 4 6
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 6
        dmi wen, addr 1 0
        write ctrl reg 16 0
        dmi wen, addr 0 1
        dmi wen, addr 0 1
        dmi wen, addr 0 2
        dmi wen, addr 0 1
        dmi wen, addr 0 2
        dmi wen, addr 0 1
        dmi wen, addr 0 2
        dmi wen, addr 0 1
        dmi wen, addr 0 2
Traceback (most recent call last):
  [snip]
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 98, in jtag_srv
    data = dut.s.jtagremote_server_recv(tdo)
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 169, in jtagremote_server_recv
    data = ord(data) - ord('0')
TypeError: ord() expected a character, but string of length 0 found
```


```
./debug/test/openocd_test.sh
Open On-Chip Debugger 0.10.0+dev-01423-g3ffa14b04-dirty (2020-10-11-15:19)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
Info : only one transport option; autoselect 'jtag'
Warn : libresoc.tap: nonstandard IR value
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:44853
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Info : JTAG tap: libresoc.tap tap/device found: 0x000018ff (mfg: 0x47f (<invalid>), part: 0x0001, ver: 0x0)
Warn : gdb services need one or more targets defined
svf processing file: "debug/test/idcode_test2.svf"
STATE RESET IDLE;
TIR 0 ;
HIR 5 TDI (1f) SMASK (1f) ;
TDR 0 ;
SIR 4 TDI (1) SMASK (f) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
SIR 4 TDI (8) SMASK (f) ;
SDR 8 TDI (0) SMASK (ff) ;
SIR 4 TDI (9) SMASK (f) ;
SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (0000000000000004) MASK (ffffffffffffffff) ;
SIR 4 TDI (8) SMASK (f) ;
SDR 8 TDI (0) SMASK (ff) ;
SIR 4 TDI (a) SMASK (f) ;
SDR 64 TDI (0000000000000002) SMASK (ffffffffffffffff) TDO (0000000000000004) MASK (ffffffffffffffff) ;
SIR 4 TDI (8) SMASK (f) ;
SDR 8 TDI (0) SMASK (ff) ;
SIR 4 TDI (9) SMASK (f) ;
SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (0000000000000002) MASK (ffffffffffffffff) ;
SIR 4 TDI (8) SMASK (f) ;
SDR 8 TDI (3) SMASK (ff) ;
SIR 4 TDI (9) SMASK (f) ;
SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (ffffffffffffffff) ;
Error: tdo check error at line 37
Error:     READ = 0x000000000000004
Error:     WANT = 0x000000000000002
Error:     MASK = 0xffffffffffffffff
Time used: 0m0s348ms 
svf file programmed failed
Info : remote_bitbang interface quit
```


```
python3 test_jtag_tap_srv.py server talking to `./debug/test/openocd_test.sh`
running server only as requested, use openocd remote to test
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 1 0
        write ctrl reg 2 4
        dmi wen, addr 0 1
        dmi wen, addr 0 0
        read ctrl reg 4
        dmi wen, addr 0 1
        dmi wen, addr 0 3
        read msr reg
Traceback (most recent call last):
  [snip]
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 98, in jtag_srv
    data = dut.s.jtagremote_server_recv(tdo)
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 169, in jtagremote_server_recv
    data = ord(data) - ord('0')
TypeError: ord() expected a character, but string of length 0 found
```
Comment 17 Luke Kenneth Casson Leighton 2020-10-21 22:49:03 BST
(In reply to Cole Poirier from comment #16)

> I'm a bit confused by your commit. It looks like you're changing the values,
> for the print statements from ("pad.i", yield xxx.pad.i) to ("pad.i", yield
> xxx.core.i)... How is it that the value of pad.i is actually that of core.i?

don't know.  it's how staf's TAP interface works.  it matches what is in Staf's unit test.

> Also, it looks like we need some more help from Cesar as the tests still
> fail.
> 
> ```
> python3 test_jtag_tap.py 

>     assert status == 0
> AssertionError
> ```
>

this is unfinished / abandoned.
Comment 18 Cole Poirier 2020-10-22 00:04:43 BST
(In reply to Luke Kenneth Casson Leighton from comment #17)
> (In reply to Cole Poirier from comment #16)
>
> > python3 test_jtag_tap.py 
> this is unfinished / abandoned.

Ok. Here's the relevant openocd_test.sh error:

```
./debug/test/openocd_test.sh
[snip]
SIR 4 TDI (8) SMASK (f) ;
SDR 8 TDI (3) SMASK (ff) ;
SIR 4 TDI (9) SMASK (f) ;
SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (00000000deadbeef) MASK (ffffffffffffffff) ;
Error: tdo check error at line 37
Error:     READ = 0x000000000000004
Error:     WANT = 0x000000000000002
Error:     MASK = 0xffffffffffffffff
Time used: 0m0s348ms 
svf file programmed failed
Info : remote_bitbang interface quit
```


```
python3 test_jtag_tap_srv.py server talking to `./debug/test/openocd_test.sh`
running server only as requested, use openocd remote to test
[snip]
        dmi wen, addr 0 1
        dmi wen, addr 0 3
        read msr reg
Traceback (most recent call last):
  [snip]
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 98, in jtag_srv
    data = dut.s.jtagremote_server_recv(tdo)
  File "/home/colepoirier/src/soc/src/soc/debug/jtagutils.py", line 169, in jtagremote_server_recv
    data = ord(data) - ord('0')
TypeError: ord() expected a character, but string of length 0 found
```
Comment 19 Cole Poirier 2020-10-22 00:10:00 BST
(In reply to Cole Poirier from comment #18)

> Ok. Here's the relevant openocd_test.sh error:
[snip]

Actually also get an error running the test that is supposed to be fixed too:

```command run: `python3 test_jtag_tap_srv.py`
dmi ctrl status 0x4
        dmi wen, addr 0 0
        read ctrl reg 6
        dmi wen, addr 0 1
dmi ctrl status 0x6
Traceback (most recent call last):
[snip]
  File "test_jtag_tap_srv.py", line 191, in jtag_sim
    assert status == 0
AssertionError
```