a full review of the reset state is needed including ensuring and confirming by unit tests that it can be pulled externally and via JTAG.
Another thing to verify is that you don't depend on the verilog initial section. A difference between FPGA and ASIC is that most FPGAs embed the initial state of the registers in their bitstream and on ASIC registers will have a random value after power-up. Or said otherwise for ASICs setting a value of a register in the initial section is ignored. I guess, but am not 100% sure that in nmigen you can only have problems if you use reset_less signals as you will always assume a reset is applied to an ASIC after power-up. One of the problems is that pysim has the FPGA behaviour on reset_less signals and not the ASIC one. That was a few months ago so I don't know if that has changed. This means that pysim/cxxsim unit tests may not reveal problems for ASICs with reset_less signals.
(In reply to Staf Verhaegen from comment #1) > I guess, but am not 100% sure that in nmigen you can only have problems if > you use reset_less signals as you will always assume a reset is applied to > an ASIC after power-up. One of the problems is that pysim has the FPGA > behaviour on reset_less signals and not the ASIC one. That was a few months > ago so I don't know if that has changed. This means that pysim/cxxsim unit > tests may not reveal problems for ASICs with reset_less signals. litex compiles with verilator, and that runs ok (although i did run into problems the first time, which i sorted). i've only used nmigen reset_less signals where it's known not to matter. thank you for highlighting this, it'll be something important to check.
Resource about ASIC resets: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf