Bug 514 - review ls180 reset connections
Summary: review ls180 reset connections
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: High enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 383
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Reported: 2020-10-07 14:17 BST by Luke Kenneth Casson Leighton
Modified: 2020-10-08 00:01 BST (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2020-10-07 14:17:36 BST
a full review of the reset state is needed
including ensuring and confirming by unit tests that it can be pulled externally and via JTAG.
Comment 1 Staf Verhaegen 2020-10-07 15:25:49 BST
Another thing to verify is that you don't depend on the verilog initial section.
A difference between FPGA and ASIC is that most FPGAs embed the initial state of the registers in their bitstream and on ASIC registers will have a random value after power-up. Or said otherwise for ASICs setting a value of a register in the initial section is ignored.

I guess, but am not 100% sure that in nmigen you can only have problems if you use reset_less signals as you will always assume a reset is applied to an ASIC after power-up. One of the problems is that pysim has the FPGA behaviour on reset_less signals and not the ASIC one. That was a few months ago so I don't know if that has changed. This means that pysim/cxxsim unit tests may not reveal problems for ASICs with reset_less signals.
Comment 2 Luke Kenneth Casson Leighton 2020-10-07 15:33:47 BST
(In reply to Staf Verhaegen from comment #1)

> I guess, but am not 100% sure that in nmigen you can only have problems if
> you use reset_less signals as you will always assume a reset is applied to
> an ASIC after power-up. One of the problems is that pysim has the FPGA
> behaviour on reset_less signals and not the ASIC one. That was a few months
> ago so I don't know if that has changed. This means that pysim/cxxsim unit
> tests may not reveal problems for ASICs with reset_less signals.

litex compiles with verilator, and that runs ok (although i did run into
problems the first time, which i sorted).  i've only used nmigen
reset_less signals where it's known not to matter.

thank you for highlighting this, it'll be something important to check.
Comment 3 Luke Kenneth Casson Leighton 2020-10-08 00:01:46 BST
Resource about ASIC resets: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf