Bug 515 - confirm that it is possible to upload into SRAM via JTAG (firmware upload / processor start script)
Summary: confirm that it is possible to upload into SRAM via JTAG (firmware upload / p...
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: High enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 383
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Reported: 2020-10-07 14:25 BST by Luke Kenneth Casson Leighton
Modified: 2020-10-10 15:46 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2020-10-07 14:25:16 BST
procedure:

* pull JTAG DMI "terminate"
* pull JTAG DMI "core reset"
* upload into SRAM memory over JTAG WB
* pull JTAG DMI "I-cache sync"
* pull JTAG DMI "core start"

script must use the openocd jtagremote functions and take two arguments: the start address to upload data to (defaults to 0x00000000) and the name of the (binary formatted) file to upload.
Comment 1 Luke Kenneth Casson Leighton 2020-10-07 14:34:37 BST
jtagremote client-server demo / unit test showing how this is done

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap_srv.py;hb=HEAD

DMI registers (DMI.CTRL) showing which bits need to be written to call "halt", stop, and start.  also probably a good idea to send "icache sync".

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi.py;hb=HEAD#l30

note that after sending JTAG DMI READ or WRITE-READ the DMI address is *automatically* incremented to the next DMI address.  this to save having to repeatedly set the DMI address and thus saving JTAG bandwidth.

the same thing is done for JTAG WB.
Comment 2 Luke Kenneth Casson Leighton 2020-10-10 15:16:23 BST
very slow (over jtagremote) but it is working: SRAM can be written and
read.

commit 4a55374a35da5c7961facf90e178353a15c6d614 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sat Oct 10 15:13:38 2020 +0100

    add first version of firmware uploader
Comment 3 Luke Kenneth Casson Leighton 2020-10-10 15:46:17 BST
commit 8d6b1f274788963d620a144593404bac96724657 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sat Oct 10 15:45:59 2020 +0100

    add DMI status / reset to firmware upload script