procedure: * pull JTAG DMI "terminate" * pull JTAG DMI "core reset" * upload into SRAM memory over JTAG WB * pull JTAG DMI "I-cache sync" * pull JTAG DMI "core start" script must use the openocd jtagremote functions and take two arguments: the start address to upload data to (defaults to 0x00000000) and the name of the (binary formatted) file to upload.
jtagremote client-server demo / unit test showing how this is done https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/test/test_jtag_tap_srv.py;hb=HEAD DMI registers (DMI.CTRL) showing which bits need to be written to call "halt", stop, and start. also probably a good idea to send "icache sync". https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi.py;hb=HEAD#l30 note that after sending JTAG DMI READ or WRITE-READ the DMI address is *automatically* incremented to the next DMI address. this to save having to repeatedly set the DMI address and thus saving JTAG bandwidth. the same thing is done for JTAG WB.
very slow (over jtagremote) but it is working: SRAM can be written and read. commit 4a55374a35da5c7961facf90e178353a15c6d614 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat Oct 10 15:13:38 2020 +0100 add first version of firmware uploader
commit 8d6b1f274788963d620a144593404bac96724657 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Sat Oct 10 15:45:59 2020 +0100 add DMI status / reset to firmware upload script