Bug 544 - assessment of OpenPOWER SIMD instructions (misnamed "vector")
Summary: assessment of OpenPOWER SIMD instructions (misnamed "vector")
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2020-12-08 12:54 GMT by Luke Kenneth Casson Leighton
Modified: 2020-12-08 12:54 GMT (History)
1 user (show)

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NLnet milestone: NLNet.2019.10.Standards
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Description Luke Kenneth Casson Leighton 2020-12-08 12:54:35 GMT
an examination of the OpenPOWER SIMD instructions is needed. 
to be recorded at https://libre-soc.org/openpower/simd_vsx/

VSX cannot strictly be called "Vector" because vectors are variable-length,
where VSX is fixed-length (i.e. SIMD).

preliminary investigation shows the inclusion of:

* DSP-style integer clamp/saturate operations
* pixel-style data reordering (in and out of 16 RGB and 32-bit formats)
* a very good type of rotate that reads a mask from part of a register
* min/max selection on both integer and FP
* FP estimation functions (log, exp, recp, rsqrt) and associated
  error estimation
* FP extraction and insertion of exponent and mantissa from/into integers 
* FP single to double precision conversion.
* Rijndael FIPS-197 and SHA-256/512 primitives
* there are some bitmanip operations that also seem not to be
  vector operations, but are more along the lines of taking advantage
  of the fact that the VSX registers are 128 bit

even the operations labelled "vector permute" are a form of 128-bit bitmanip
operating at the byte level (i.e. not vector).

the only operations that could conceivably be called "vector" are 
the vector extract/insert and splat instructions, although, again,
these can be covered by some careful design of 128-bit bitmanip
operations.

analysis of these instructions is valuable with a view to guiding whether
and how they should be included in Simple-V