Bug 548 - modify sv_analysis.py to create new svp64 tables
Summary: modify sv_analysis.py to create new svp64 tables
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Reported: 2020-12-18 00:19 GMT by Luke Kenneth Casson Leighton
Modified: 2020-12-18 00:27 GMT (History)
3 users (show)

See Also:
NLnet milestone: NLNet.2019.10.Standards
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2020-12-18 00:19:00 GMT
the new svp64 encoding is approaching complete, for review.  with the new RM register maps these need to be applied to instructions, i.e. tables (CSV files) autogenerated.

see https://libre-soc.org/openpower/sv/svp_rewrite/svp64/

requirements: using sv_analysis.py create CSV file, one per Register Profile Type, that map the instruction onto the RM-*-* rypes and associate each register RA RB RC RT RS and BFA etc. with an REXTRA*.

this so that in the PowerDecoder it becomes possible to read those exact same CSV files for creation of the augmented SV ISA.

in addition a "support" page must be created that reads CSV files (see isatsbles.mdwn) and presents the CSV data as wiki tables for easy reading.