Note I meant specifically for gather-load and scatter-store, where the base register is marked as a vector and when mode is set to fail-on-first, we would instead interpret that as a strided load/store with a scalar base register, since otherwise we wouldn't have an encoding for that.

(In reply to Jacob Lifshay from comment #1)
> Note I meant specifically for gather-load and scatter-store, where the base
> register is marked as a vector and when mode is set to fail-on-first, we
> would instead interpret that as a strided load/store with a scalar base
> register, since otherwise we wouldn't have an encoding for that.

strided load would mean something like:

for(i = 0; i < VL; i++)
    reg[rt + i] = mem[reg[ra] + i * imm];

(In reply to Jacob Lifshay from comment #2)
> strided load would mean something like:
> 
> for(i = 0; i < VL; i++)
>     reg[rt + i] = mem[reg[ra] + i * imm];

we will want imm to be signed

(In reply to Jacob Lifshay from comment #3)
> (In reply to Jacob Lifshay from comment #2)
> > strided load would mean something like:
> > 
> > for(i = 0; i < VL; i++)
> >     reg[rt + i] = mem[reg[ra] + i * imm];
> 
> we will want imm to be signed

that's an immediate variant - RA(D) - which is
already covered and separate and distinct from
Indexed variant (RA + RB).

it's looking like this one's an invalid bugreport
because ffirst *indexed* was supposed to be banned,
then used for sonething else, but it cannot be
an immediate-strided instruction because there is
no immediate.

it *could* however be used for

for(i = 0; i < VL; i++)
   reg[rt + i] = mem[reg[ra] + i * reg[rb]];

as long as RB is a scalar.

(In reply to Luke Kenneth Casson Leighton from comment #4)
> 
> it *could* however be used for
> 
> for(i = 0; i < VL; i++)
>    reg[rt + i] = mem[reg[ra] + i * reg[rb]];

ah, yeah, that's what I was thinking of.

(In reply to Jacob Lifshay from comment #5)

> ah, yeah, that's what I was thinking of.

i can see how it'd be useful, particularly as it only
needs 2 reg reads but feeds a Vector result.  now have to come up
with a name for it, sigh.

    sv.ld/str  RT.v, RA, RB

(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #5)
> 
> > ah, yeah, that's what I was thinking of.
> 
> i can see how it'd be useful, particularly as it only
> needs 2 reg reads but feeds a Vector result.  now have to come up
> with a name for it, sigh.
> 
>     sv.ld/str  RT.v, RA, RB

ld-indexed-strided