Bug 563 - 128-bit instructions and SimpleV
Summary: 128-bit instructions and SimpleV
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 213
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Reported: 2020-12-30 19:27 GMT by Jacob Lifshay
Modified: 2022-07-31 23:53 BST (History)
1 user (show)

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Description Jacob Lifshay 2020-12-30 19:27:26 GMT 
I think we should support 128-bit elements symmetrically to 64/32/16/8-bit operations by just having the 128-bit vsx instruction be the base instruction that gets prefixed, this would mean subvl=1 has 128-bit subvectors, subvl=2 has 256-bit subvectors, 3 for 384-bit, and 4 for 512-bit.

this is because it doesn't make sense to have an instruction for a 64-bit half of a intrinsically 128-bit operation such as f128 add.
Comment 1 Luke Kenneth Casson Leighton 2020-12-30 19:44:34 GMT 
conceptually i like it.  especially the symmetry and being able to apply sub-vectoring to 128-bit operations.  it's waaay advanced and in the future though :)
Comment 2 Jacob Lifshay 2020-12-30 19:54:38 GMT 
(In reply to Luke Kenneth Casson Leighton from comment #1)
> conceptually i like it.  especially the symmetry and being able to apply
> sub-vectoring to 128-bit operations.  it's waaay advanced and in the future
> though :)

maybe not that far in the future, since aes is a 128-bit operation that we will want to support :)