see http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-January/001882.html the SPR operations all default to going to the SPR pipeline, where in this case we don't want that: we want some to go to the MMU pipeline. https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD#l728 the field you want to modify is fn_unit: use the following pattern: fu = self.op_get("function_unit") if fu is not None: if self.dec.op.internal_op == OP_MTMSR: if spr_out == {whatever}: self.do_copy("fn_unit", Function.MMU) same thing for spr in, for MFMSR
I modified the fn_unit field in my last commit, SPRs 18 and 19 now get forwarded to the MMU.
(In reply to Tobias Platen from comment #1) > I modified the fn_unit field in my last commit, SPRs 18 and 19 now get > forwarded to the MMU. excellent. do push it so we can take a look :) https://github.com/antonblanchard/microwatt/blob/5f8279a14ab2921df91babd684f6a4991c59ac29/decode1.vhdl#L587 the list that microwatt flip over is this: case sprn is when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL => vi.override_decode.unit := LDST; so that'll likely be what we'll need to do at some point (except to MMU).
excellent, saw the commits. am just doing some whitespace cleanup (please keep an eye on that). also do use the power_enums SPR class/instance to do "SPR.DSISR" (something like that) rather than hard-coded numbers that will mean nothing to people unfamiliar with the 1,300 page technical reference manual lkcl@fizzy:~/src/libresoc/soc/src/soc$ python3 decoder/power_enums.py SPR.TAR SPR.XER 1 SPR.XER XER SPR.DSCR 3 SPR.DSCR DSCR SPR.LR 8 SPR.LR LR SPR.CTR 9 SPR.CTR CTR SPR.AMR 13 SPR.AMR AMR SPR.DSCR_priv 17 SPR.DSCR_priv DSCR_priv SPR.DSISR 18 SPR.DSISR DSISR SPR.DAR 19 SPR.DAR DAR commit 1f7f510c9b03d3646a52153874b37f33062b9ae5 (HEAD -> master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Wed Jan 27 12:35:30 2021 +0000 whitespace and shortening of SPR MMU redirection in Power Decoder
I also need to redirect the SPR number and op.internal_op to the MMU FSM. When executing an MTSPR instruction that belongs to the MMU, the FSM sees OP_ILLEGAL instead of an OP_MTSPR. I'm currently investigating why.
(In reply to Tobias Platen from comment #4) > I also need to redirect the SPR number and op.internal_op to the MMU FSM. > When executing an MTSPR instruction that belongs to the MMU, the FSM sees > OP_ILLEGAL instead of an OP_MTSPR. I'm currently investigating why. this is possibly because the unit test is not setting the MSR correctly and instr_is_priv is firing. comment it out temporarily to check if that's the case.
tobias note this: for i, x in enumerate(SPR): vvvvv with m.Case(x.value): <<========== ^^^^^ m.d.comb += self.spr_o.data.eq(i) m.d.comb += self.spr_o.ok.eq(1) which is not being done here: ((spr == SPR.DSISR) | (spr == SPR.DAR))):
fixed
My unit test for the MMU passes, SPRs are now redirected correctly.
(In reply to Tobias Platen from comment #8) > My unit test for the MMU passes, SPRs are now redirected correctly. fantastic! i thought it might be the enum thing. i have no idea why nmigen does not detect / compare automatically against the value in an Auto-Enum, but hey.