Bug 586 - microwatt SVP64-equivalent of decode1.vhdl to be autogenerated
Summary: microwatt SVP64-equivalent of decode1.vhdl to be autogenerated
Alias: None
Product: Libre-SOC Website
Classification: Unclassified
Component: website (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/im...
Depends on:
Reported: 2021-01-28 15:58 GMT by Luke Kenneth Casson Leighton
Modified: 2021-03-18 12:40 GMT (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2021-01-28 15:58:25 GMT
a variant of the SVP64RM class is needed which auto-generates
a convenient CSV-like version of decode1.vhdl with the fields
needed to decode SVP64 "EXTRA" (register) parts of svp64 prefix.

TODO: move RS from in1 to in3 in an automated fashion (DONE)
Comment 1 Luke Kenneth Casson Leighton 2021-02-27 14:58:01 GMT
started here:


preliminary output here (pending data structures / types)


it should match precisely with the array lengths from decode1.vhdl, and the idea is that in decode2.vhdl wherever a decode_rom_t is used then a corresponding sv_decode_rom_t is also used.

if there is no entry and yet the instruction is SVP64-prefixed then an illegal instruction exception must be raised.
Comment 2 Luke Kenneth Casson Leighton 2021-02-28 11:08:34 GMT
cross-reference discussion


that was an alteration to sv_analysis.py to, instead of having a series of register names that are hard to look up, match up with decode1.vhdl in1/2/3 and make it easy to identify.
Comment 3 Luke Kenneth Casson Leighton 2021-03-18 12:40:10 GMT
commit 00c03aad232bdfb4cf20d6afec12247b91105f97 (HEAD -> master, origin/master, origin/HEAD)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Thu Mar 18 12:36:46 2021 +0000

    update microwatt sv_decode.vhdl prototype with new sv_out2 column


two changes:

1) the RS has been moved
2) a new "out2" column has been added including which EXTRA2/3 is used
   to extend it