a variant of the SVP64RM class is needed which auto-generates a convenient CSV-like version of decode1.vhdl with the fields needed to decode SVP64 "EXTRA" (register) parts of svp64 prefix. TODO: move RS from in1 to in3 in an automated fashion (DONE)
started here: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD preliminary output here (pending data structures / types) https://ftp.libre-soc.org/sv_decode.vhdl it should match precisely with the array lengths from decode1.vhdl, and the idea is that in decode2.vhdl wherever a decode_rom_t is used then a corresponding sv_decode_rom_t is also used. if there is no entry and yet the instruction is SVP64-prefixed then an illegal instruction exception must be raised.
cross-reference discussion http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2021-February/000247.html that was an alteration to sv_analysis.py to, instead of having a series of register names that are hard to look up, match up with decode1.vhdl in1/2/3 and make it easy to identify.
commit 00c03aad232bdfb4cf20d6afec12247b91105f97 (HEAD -> master, origin/master, origin/HEAD) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Mar 18 12:36:46 2021 +0000 update microwatt sv_decode.vhdl prototype with new sv_out2 column https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=00c03aad232bdfb4cf20d6afec12247b91105f97 two changes: 1) the RS has been moved 2) a new "out2" column has been added including which EXTRA2/3 is used to extend it