Consider the pseudo-code for register number augmentation: https://libre-soc.org/openpower/sv/svp64/#index13h1 Accorting to the tables below, it seems that the bit for scalar/vector selection in "spec" is intended to be its MSB. So, in MSB0 notation, it should be spec[0], not spec[2]. The augmentation bits then are the two less significant, so it should be spec[1:2], not spec[0:1]. In other words: if extra3_mode: spec = EXTRA3 else: spec = EXTRA2 << 1 # same as EXTRA3, shifted if spec[0]: # vector (MSB of spec) return (RA << 2) | spec[1:2] else: # scalar return (spec[1:2] << 5) | RA
Created attachment 126 [details] Proposed fixes for MSB0 issues in pseudo-code After a review of SVP64 register remapping documentation, I found these places where LSB0 numbering was being used in pseudo-code. OK to commit?
Comment on attachment 126 [details] Proposed fixes for MSB0 issues in pseudo-code ah ok in the spec? yes go for it. i will try not to cry into my tea too much. ok i'm done. commit it :)
(In reply to Luke Kenneth Casson Leighton from comment #2) > ah ok in the spec? yes go for it. i will try not to cry into my tea too > much. ok i'm done. commit it :) Done.