Bug 642 - reduce width of input records by sending only required bits of state / data
Summary: reduce width of input records by sending only required bits of state / data
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2021-05-11 11:40 BST by Luke Kenneth Casson Leighton
Modified: 2021-05-11 11:40 BST (History)
1 user (show)

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Description Luke Kenneth Casson Leighton 2021-05-11 11:40:58 BST 
example, in ldst input record:

                  ('msr', 64), # TODO: a lot less bits.  only need PR

also in MMU, and other locations: frequently it is only a few bits
that are needed.  strictly speaking, MSR should be subdivided into
its own regfile by "bits"