Bug 648 - TestIssue failures in BranchTestCase()
Summary: TestIssue failures in BranchTestCase()
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2021-05-18 12:29 BST by Cesar Strauss
Modified: 2021-05-18 14:22 BST (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Attachments

Note You need to log in before you can comment on or make changes to this bug.
Description Cesar Strauss 2021-05-18 12:29:45 BST
The BranchTestCase() test suite in TestIssuer began failing after this commit:

commit a1698c4d20d224c32daab1e5f41dab53add1d262
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon May 17 16:33:31 2021 +0100

    update reg sort order in ISACaller

 src/openpower/decoder/isa/caller.py | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

I did run:

$ make pyfnwriter
$ make pywriter

The commit before it runs OK.

The GeneralTestCase() also fails, on the test_loop case.

======================================================================
FAIL: run_all (soc.simple.test.test_runner.TestRunner) [test_loop]
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/cstrauss/src/soc/src/soc/simple/test/test_runner.py", line 299, in process
    yield from check_regs(self, sim, core, test, code)
  File "/home/cstrauss/src/soc/src/soc/simple/test/test_core.py", line 175, in check_regs
    "cr reg %d not equal %s" % (i, repr(code)))
AssertionError: 0 != 4 : cr reg 5 not equal 'bc 4,10,-8'

There seems to be some issue with branches.
Comment 1 Luke Kenneth Casson Leighton 2021-05-18 12:47:53 BST
yep confirmed, this will be due to the ISACaller register order
changing from how it's declared in the instruction.

i think, only overflow should be re-ordered.
Comment 2 Luke Kenneth Casson Leighton 2021-05-18 12:56:58 BST
got it, reverted, and pushed.  please double-check. thanks Cesar.
Comment 3 Cesar Strauss 2021-05-18 14:22:05 BST
It works!

I'm closing the bug.