we completely missed that bc uses CR fields, and thus could
be SVP64 Vectorised.
* design pretty much done
* added SVP64 24-bit RM decoder
* added sv_analysis to include bc and bclr SVP64 EXTRA modes
commit 4ad3c373c7fbd826447de0c64b558eeb2b53d174 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <firstname.lastname@example.org>
Date: Sun Aug 8 22:06:45 2021 +0100
add start of SVP64ASM encoder for sv.bc and sv.bclr
TODO, sv.bca, sv.bclrl etc.
svstep mode looks like it is too "CISC-like". although remarkably
similar to CTR auto-decrement, svstep auto-increment involves predicate
skipping as well as REMAP. realistically this is too much, unfortunately.
currently implementing sv.bc in ISACaller, this is the first time that
CR fields have been involved.
it would have been much better to have started with sv.crand (etc)
before trying to do sv.bc because then the infrastructure for read/write
of CR Fields would already be in place.
realistically, the pseudocode needs to change from