Bug 664 - design SVP64 branch instructions (sv.bc)
Summary: design SVP64 branch instructions (sv.bc)
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/br...
Depends on:
Blocks: 213
  Show dependency treegraph
 
Reported: 2021-08-01 19:20 BST by Luke Kenneth Casson Leighton
Modified: 2021-10-03 22:22 BST (History)
1 user (show)

See Also:
NLnet milestone: NLNet.2019.10.Standards
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


Attachments

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2021-08-01 19:20:06 BST
we completely missed that bc uses CR fields, and thus could
be SVP64 Vectorised.

http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html
Comment 1 Luke Kenneth Casson Leighton 2021-08-08 15:57:25 BST
* design pretty much done
* added SVP64 24-bit RM decoder
* added sv_analysis to include bc and bclr SVP64 EXTRA modes
Comment 2 Luke Kenneth Casson Leighton 2021-08-08 22:06:57 BST
commit 4ad3c373c7fbd826447de0c64b558eeb2b53d174 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Sun Aug 8 22:06:45 2021 +0100

    add start of SVP64ASM encoder for sv.bc and sv.bclr
    TODO, sv.bca, sv.bclrl etc.
Comment 3 Luke Kenneth Casson Leighton 2021-08-12 16:10:26 BST
svstep mode looks like it is too "CISC-like".  although remarkably
similar to CTR auto-decrement, svstep auto-increment involves predicate
skipping as well as REMAP.  realistically this is too much, unfortunately.

currently implementing sv.bc in ISACaller, this is the first time that
CR fields have been involved.

it would have been much better to have started with sv.crand (etc)
before trying to do sv.bc because then the infrastructure for read/write
of CR Fields would already be in place.

realistically, the pseudocode needs to change from

   CR[BI+32]

to

    CRF(BI[0:2])[BI[3:4]