Bug 683 - possible precedence error in divw XLEN
Summary: possible precedence error in divw XLEN
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 671
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Reported: 2021-09-03 08:43 BST by Luke Kenneth Casson Leighton
Modified: 2021-09-03 08:50 BST (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2021-09-03 08:43:19 BST 
-    dividend[0:31] <- (RA)[32:63]
-    divisor[0:31] <- (RB) [32:63]
-    if (((dividend = 0x8000_0000) &
-         (divisor = [1]*32)) |
-         (divisor = [0]*32)) then
-        RT[0:63] <- undefined([0]*64)
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
+    divisor[0:(XLEN/2)-1] <- (RB) [XLEN/2:XLEN-1]
+    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
+         (divisor = [1]*XLEN/2)) |
+         (divisor = [0]*XLEN/2)) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)

[1]*XLEN/2 *may* be being interpreted as:

   ([1]*XLEN)/2
Comment 1 Luke Kenneth Casson Leighton 2021-09-03 08:47:03 BST 
    concat(1, repeat=XLEN) // 2) | eq(divisor, concat(0, repeat=XLEN) // 2):

yes, it's definitely producing concat(1, repeat=XLEN)/2

rather than the correct

   concat(1, repeat=XLEN/2)
Comment 2 Luke Kenneth Casson Leighton 2021-09-03 08:49:24 BST 
commit 907452d23734f8cc4bd65b87a8019a912d19cacd (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Fri Sep 3 08:49:13 2021 +0100

    use brackets round (XLEN/2) in divw pseudocode
    [0]*XLEN/2 was being interpreted as ([0]*XLEN)/2