Bug 699 - Draft Release v0.1 of SVP64
Summary: Draft Release v0.1 of SVP64
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/openpower/sv/sv...
Depends on:
Blocks: 213
  Show dependency treegraph
Reported: 2021-09-18 12:56 BST by Luke Kenneth Casson Leighton
Modified: 2022-06-16 09:53 BST (History)
2 users (show)

See Also:
NLnet milestone: NLNet.2019.10.046.Standards
total budget (EUR) for completion of task and all subtasks: 5500
budget (EUR) for this task, excluding subtasks' budget: 5500
parent task for budget allocation: 213
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
jacob = { amount = 1200, paid = 2021-10-20 } [lkcl] amount = 4300 submitted = 2021-12-09 paid = 2021-12-09


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Description Luke Kenneth Casson Leighton 2021-09-18 12:56:22 BST
First Draft release of SVP64 Standard. Based conceptually on
an x86-like "REP-" Prefixing of the Scalar Power ISA v3.0B,
Draft SVP64 brings the Power ISA up-to-date with advanced
Supercomputing Vector Processing capabilities suited to
High Performance Compute, 3D GPU, Video, Scientific
and traditional DSP Workloads. With over 3 years of
development of the Draft 0.1 Specification, Features include:

* 24 bit prefix format for 64 bit Vector operations
  that fits within the Power ISA v3.1 64 bit Prefix
* Vector Lengths up to 64 elements
* Element-width Overrides (polymorphism) for both
  source and destination registers, bringing
  FP16 and BF16 Vectors to the Power ISA
* Extending Register File sizes to suit 3D and Video
  - 128 64-bit Integers,
  - 128 64-bit Floating-Point
  - 128 Condition Register Fields primarily for use as
    Predicate Masks
* Sub-vectors (vec2/3/4) suited to 3D GPU workloads
  and Audio/Visual processing
* Single and Twin Predication (back-to-back VREDUCE
* 4 different Mode variants: Arithmetic/Logical,
  CR ops, Branch-Conditional and LD/ST. Similar
  to Power ISA v3.1 MTRR/MLS Prefix types providing:
  - Arithmetic Saturation
  - Fail-First (Speculative LD/ST)
  - Data-dependent Fail-First
  - Deterministic Scalar and Parallel Reduction
    and Iteration
  - "Predicate-result" (result is dropped if CR Field
    test fails)
* REMAP Scheduling for arbitrary-sized Matrices, and
  triple loop DCT and FFT. Size is limited by size
  of Register File.
* Both Horizontal-First (Cray) and Vertical-First
  (Mitch Alsup MyISA 66000) Vectorisation Modes

Draft Specification at:

Funded by the NLnet Foundation under their Privacy and
Enhanced Trust Programme, as a Work for the Public Good.
SVP64 is to be submitted to the newly-formed OpenPOWER
ISA Workgroup via the External RFC Process.
Comment 1 Luke Kenneth Casson Leighton 2021-09-18 19:00:04 BST

Comment 2 Jacob Lifshay 2021-09-21 02:02:51 BST
looks good enough to me, though I do (incorrectly?) remember working on the initial svp64 for more than a month...

are we going to just create a git tag and call that good?
Comment 3 Luke Kenneth Casson Leighton 2021-09-21 17:09:27 BST
(In reply to Jacob Lifshay from comment #2)
> looks good enough to me, though I do (incorrectly?) remember working on the
> initial svp64 for more than a month...

unnfortunately, i screwed up the scale / estimates on this one.
i've been constantly editing and reading for several hours a day
most days for what must be 10 months straight and there's no way
that's only EUR 3850 worth of work. it may be we have to reluctantly
scale back the other donations (reallocate some to you and i)

i've a StandICT Grant Request in, for EUR 10,000, however it is
for specific tasks such as writing presentations rather than retrospective.
i.e. needs actual extra work to be done.

> are we going to just create a git tag and call that good?

yeah good point.  done, DRAFT_SVP64_0_1