Bug 743 - TestIssuer does not terminate in svp64 mode test_issuer_svp64.py
Summary: TestIssuer does not terminate in svp64 mode test_issuer_svp64.py
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on:
Reported: 2021-11-08 11:30 GMT by Luke Kenneth Casson Leighton
Modified: 2021-11-08 11:31 GMT (History)
2 users (show)

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Description Luke Kenneth Casson Leighton 2021-11-08 11:30:46 GMT
in commit f25faf58a3ed81 the test runner was converted to a new API
which, instead of running single-step concurrently HDL-Simulator instruction 1,
HDL-Simulator instruction 2, .... it is now HDL instruction 1, HDL instruction 2
... followed separately by Simulator instruction 1, Simulator instruction 2 ...

HDL in SVP64 is not correctly detecting a terminating condition, instead
entering a permanent loop.  test_runner.py:

            terminated = yield self.issuer.dbg.terminated_o

this is never being set (in svp64 mode) and therefore the HDL simulation
never terminates.