Bug 75 - create an IEEE754 FP "add" pipeline
Summary: create an IEEE754 FP "add" pipeline
Status: PAYMENTPENDING FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 48
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Reported: 2019-04-26 21:35 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-06 14:27 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLnet.2019.02.012
total budget (EUR) for completion of task and all subtasks: 1500
budget (EUR) for this task, excluding subtasks' budget: 1500
parent task for budget allocation: 48
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=1500, paid=2019-06-04}

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Description Luke Kenneth Casson Leighton 2019-04-26 21:35:30 BST 
an IEEE754 FP pipelined "add" is needed which can do FP16/32/64