Bug 76 - IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed
Summary: IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed
Status: RESOLVED INVALID
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 48
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Reported: 2019-04-26 21:38 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-06 11:56 GMT (History)
1 user (show)

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NLnet milestone: NLnet.2019.02.012
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Description Luke Kenneth Casson Leighton 2019-04-26 21:38:50 BST 
RISC-V has some specific "quirks" in its handling of rounding,
tininess and NaN handling, which need to be specifically catered for.
Comment 1 Luke Kenneth Casson Leighton 2019-08-10 06:50:45 BST 
http://www.jhauser.us/arithmetic/HardFloat-1/doc/HardFloat-Verilog.html
http://www.jhauser.us/arithmetic/HardFloat.html

source is a .zip archive.  there is an extremely clean and clear function,
roundRawFNtoRecFN in there which has all of the logic for rounding.
Comment 2 Luke Kenneth Casson Leighton 2020-12-06 11:56:19 GMT 
not doing RISC-V.