Bug 77 - IEEE754 FP "mul" needed
Summary: IEEE754 FP "mul" needed
Status: PAYMENTPENDING FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: ALU (including IEEE754 16/32/64-bit FPU) (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on: 60
Blocks: 48
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Reported: 2019-04-26 21:41 BST by Luke Kenneth Casson Leighton
Modified: 2020-12-06 14:00 GMT (History)
1 user (show)

See Also:
NLnet milestone: NLnet.2019.02
total budget (EUR) for completion of task and all subtasks: 4500
budget (EUR) for this task, excluding subtasks' budget: 2000
parent task for budget allocation: 48
child tasks for budget allocation: 60
The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=2000, paid=2019-07-10}


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Description Luke Kenneth Casson Leighton 2019-04-26 21:41:01 BST
an IEEE754 FP "multiply" pipeline is needed, for FP16/32/64.
also needed is the optional ability to specify how many stages
the actual multiplication is to take
Comment 1 Luke Kenneth Casson Leighton 2019-05-03 07:41:27 BST
FP16 mul pipeline bug:
* 0xe7bb 0x81ce 0x2afa (returns 0x2af9)
* 0x113 0xf569 0xb5d0 (returns 0xb5ce)
Comment 2 Luke Kenneth Casson Leighton 2019-07-14 14:22:17 BST
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fpmul/align.py;h=6fea67ca13d168b0050cef93591c9d8f2f1056e3;hb=13417cb39c9dc37e5472555934dd27b39aa5b5ed#l72

found source of inaccuracy: alignment (pre-normalisation) of a and b
were entirely misssing!

unit tests pass, ran several tens of thousands of tests on FP16, FP32
and FP64.