Bug 796 - Tercel SPI PHY POR reset fails under certain conditions
Summary: Tercel SPI PHY POR reset fails under certain conditions
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Other
: --- normal
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2022-04-02 20:26 BST by tpearson
Modified: 2022-04-02 20:26 BST (History)
1 user (show)

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Description tpearson 2022-04-02 20:26:26 BST 
Under specific conditions with a short (relative to SPI clock) power on reset pulse, the Tercel SPI controller PHY may fail to reset, leading to undefined behavior until an external reset is triggered.

This is fixed in GIT hash bf4f580 (microwatt).