Bug 827 - 2RW SRAM cell design; 1RW SRAM cell improvement
Summary: 2RW SRAM cell design; 1RW SRAM cell improvement
Status: RESOLVED INVALID
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Staf Verhaegen
URL:
Depends on:
Blocks: 690
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Reported: 2022-05-02 14:09 BST by Staf Verhaegen
Modified: 2022-08-29 23:09 BST (History)
2 users (show)

See Also:
NLnet milestone: NGI.POINTER.Gigabit.ASIC
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
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Description Staf Verhaegen 2022-05-02 14:09:05 BST 
For the Gigabit ASIC dual port 2RW SRAM blocks will be developed.
This task is for development of the 2RW SRAM cell. It consists of the design and layout of the cell.
Also the 1RW SRAM cell will be visited as likely the area can be reduced with w reduction of the transistors.